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The aggressive scaling of technology parameters in deep submicron (DSM) circuits has led towards an increased impact of process variations on delay and crosstalk noise. In this work, we develop a new post-layout gate sizing algorithm for simultaneous reduction of delay uncertainty and crosstalk noise under the impact of process variations. The problem of postlayout statistical gate sizing is modeled as a 2-player stochastic game and solved using Nash equilibrium theory. Due to process variations, the gate sizes are no longer deterministic, but rather behave as a probabilistic distribution over a range. Stochastic games allow the modeling of probabilistic distribution of gate size space and also effectively capture the conflicting nature of the problem. We have implemented two different strategies in which the games are ordered according to (i) the noise criticality, and (ii) the delay criticality of nets. Experimental results demonstrate the effectiveness of the developed methodology by improving both delay and crosstalk noise violations, resulting in improved yield when compared to the deterministic approach without area overhead or the need for rerouting.

In this paper, we propose a new methodology for wire sizing with simultaneous optimization of interconnect delay and crosstalk noise in deep submicron VLSI circuits. The wire sizing problem is modeled as an optimization problem formulated as a normal form game and solved using the Nash equilibrium. Game theory allows the optimization of multiple metrics with conflicting objectives. This property is exploited in modeling the wire sizing problem while simultaneously optimizing interconnect delay and crosstalk noise, which are conflicting in nature. The nets connecting the driving cell and the driven cell are divided into net segments. The net segments within a channel are modeled as players, the range of possible wire sizes forms the set of strategies and the payoff function is derived as the geometric mean of interconnect delay and crosstalk noise. The net segments are optimized from the ones closest to the driven cell towards the ones at the driving cell. The complete information about the coupling effects among the nets is extracted after the detailed routing phase. The resulting algorithm for wire sizing is linear in terms of the number of wire segments in the given circuit. Experimental results on several medium and large open core designs indicate that the proposed algorithm yields an average reduction of 21.48% in interconnect delay and 26.25% in crosstalk noise over and above the optimization from the Cadence place and route tools without any area overhead. The algorithm performs significantly better than simulated annealing and genetic search as established through experimental results. A mathematical proof of existence for Nash equilibrium solution for the proposed wire sizing formulation is provided.