LECTOR: a technique for leakage reduction in CMOS circuits

Hanchate, N.; Ranganathan, N.

doi:10.1109/tvlsi.2003.821547

Cited by 179 publications

(71 citation statements)

References 16 publications

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“…This also provides better noise margins and helps to avoid the hot carrier affects in short channel devices [3]. Scaling down threshold voltage threshold voltage results in exceptional increase in threshold leakage current [4].…”

Section: Different Concepts Of Power Dissipationmentioning

confidence: 99%

Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read and Write Enable

Alekhya¹,

Sudhakar²

2017

IOSR JVSP

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Section: Different Concepts Of Power Dissipationmentioning

confidence: 99%

Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read and Write Enable

Alekhya¹,

Sudhakar²

2017

IOSR JVSP

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“…According to [8] it is one of the most commonly known traditional approaches for sub threshold leakage power reduction is the sleep approach. In this sleep approach, additional transistors (sleep transistors) are inserted in between the power supply and ground.…”

Section: Sleep Mode Approachmentioning

confidence: 99%

“…This led to the authors in [8] to design a new better circuit and in this race they suggested a new technique called the stack technique which forces a stack effect by breaking down an existing transistor into two half size transistors. The authors suggested the circuit as shown in Figure 2.…”

Section: Stack Approachmentioning

confidence: 99%

Review of Leakage Power Reduction in CMOS Circuits

Kumari¹,

Agarwal²,

Jayvrat³

et al. 2014

AJEEE

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Recent Technological advances in Wireless Communication has shown the convergence of terminals and networks that support multimedia and real-time applications. This obviously puts an immense pressure on battery of any mobile device. The CMOS has been the leading technology in today's world of mobile communication due to its low power consumption. Reduction of leakage power in CMOS has been the research interest for the last couple of years. In CMOS integrated circuit design there is an important trade-off between technology scaling and static power consumption. In today's CMOS technology the leakage power consumption plays a significant role. As we approaching to nano-scale design the total chip power consumption becomes dependent on leakage power. Increasing the battery life in mobile wireless communication and mobile computing and similar other applications is the topic of research now-a days... Further, since the leakage of battery exists even when devices are in idle state makes leakage power loss most critical in CMOS VLSI circuits. Many techniques have been evolved to tackle the problem and its still in progress. This paper mainly focuses on the review of various works done in this field till today's date. Further a review of recent work done on a new technique LSSR (Lector Stack State Retention Technique) is discussed in the paper.

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“…The performance of our proposed LPSR technique with respect to leakage power during active and sleep modes of operation as well as total power dissipation are compared with these existing methods in Section 4. The LECTOR method [10] inserts two extra Leakage Control Transistors (a P-type and an N-type) within the gate, in which the gate terminal of each Leakage Control Transistor is controlled by the source of the other. GALEOR [11] technique reduces the leakage current flowing through the CMOS logic gate using stack effect.…”

Section: Review Of Earlier Low Leakage Power Techniquesmentioning

confidence: 99%

“…In real transistors current does not abruptly cut-off below threshold, but drops off exponentially as given by equation (1). This sub-threshold leakage current for V GS < V T is given by In these equations I DS0 is current at threshold( dependent on process and device geometry), V T0 is the zero bias threshold voltage, γ -is the linearized body effect coefficient, η represents the effect of V DS on threshold voltage, n is the sub- [4], Dual V T CMOS [5], DRG Cache [6], multiple power gating [7], sleepy keeper [8], VCLEART [9], LECTOR [10], GALLEOR [11], Sleepy Pass Gate [12], low leak stable SRAM [13], ultra low leak and state retention for inverters [14] , are some of the techniques for leakage reduction. Each method has its own merits and demerits.…”

Section: Introductionmentioning

confidence: 99%

LPSR: Novel Low Power State Retention Technique for CMOS VLSI Design

Rajani¹,

Kulkarni²

2012

IJCA

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In mobile computing and mobile communication applications powered by battery, the battery life is a premier concern. Leakage power loss is critical in CMOS VLSI circuits as it leaks the battery even when devices are in idle state. To reduce subthreshold leakage power as well as total power in CMOS logic gates and circuits a new circuit technique called LPSR Technique is proposed in this work. Earlier well known techniques for leakage reduction and state retention are compared with this technique. This technique reduces maximum amount of leakage power during deep sleep mode, maximum power reduction during dynamic (clocked) mode and has a provision of preserving state in low power sleep mode. All the circuits are designed, simulated and low power performance evaluation is done using 90nm CMOS technology files in Cadence Design Environment. General TermsCMOS VLSI Design, low power operation

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LECTOR: a technique for leakage reduction in CMOS circuits

Cited by 179 publications

References 16 publications

Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read and Write Enable

Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read and Write Enable

Review of Leakage Power Reduction in CMOS Circuits

LPSR: Novel Low Power State Retention Technique for CMOS VLSI Design

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