A New Technique to Extract the Source/Drain Series Resistance of MOSFETs

Abstract

International audienceThis letter demonstrates a new technique to extract the source/drain series resistance of MOSFETs. Unlike the well-known total resistance techniques, R sd is extracted in a way that the result is insensitive to effective length and mobility variations. The technique has been successfully applied to 45-nm bulk and fully depleted SOI MOSFETs with high-¿ and metal gate, having channel length down to 22 nm. The technique provides a high accuracy and allows fast measurements and statistical analysis

Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction

“…A lot of methods have been proposed for the MOSFET parameter extraction but they are generally restricted to the above threshold region and mostly assume that the inversion charge varies linearly with gate voltage overdrive [1][2][3][4][5][6][7][8][9][10][11]. As the supply voltage Vdd is reduced with device scaling, the operating gate bias moves closer to the threshold voltage (near threshold operation), and the assumption that the inversion charge varies approximately linearly with gate voltage overdrive becomes less and less accurate.…”

Enhanced Temperature Dependence of Phonon-Scattering-Limited Mobility in Compressively Uniaxial Strained pMOSFETs

“…The drain bias condition was 5 mV. Since external resistance R sd is crucial to mobility extraction for short-channel devices [8], [9], the BSIM R sd method [10] was adopted to extract the external resistance based on the I-V characteristics. The ideal drain current can then be derived from…”

Y-Function Analysis of the Low Temperature Behavior of Ultrathin Film FD SOI MOSFETs

“…With time, this method was proved to remain compatible with previously existing ones, avoiding second order derivative procedure, and therefore to be applicable for inline parametric test extraction in the microelectronics industry [3]. It was also improved to overcome the difficulties encountered by applying the conventional techniques [4] and was applied to more complex devices having an architecture of nanoscale double-gate transistors [5] and fully depleted SOI MOSFETs with high-and metal gate [6] and to devices in saturation regime [7]. This smart technique also permits the extraction of the gate voltage dependence of the series resistance [8].…”