A new test pattern generation method for delay fault testing

Abstract

Importance of delay testing is growing especially for high speed circuits. As delay testing using automatic test equipment is expensive, built-in self-test is an alternative technique that can significantly reduce the cost of delay testing. In this papel; a new test pattem generation method for the detection of delay faults is proposed. It can be seen as a directed random generation technique, and uses some original concepts from Machine Gaming to generate delay fault detecting test pairs. First, (a set of random test vectors is generated. Next, a learning tool working on those vectors provides relevant features of delay fault detecting test pairs. Finally, a set of new test vectors that are consistent with those features is generated. A comparison with other test generation techniques has been done on several circuits, and has shown the eflciency of our solution in terms of test sequence length and delay fault cove rage.

Designing Power-Efficient BIST Architecture: Leveraging Reversible Logic for Scalable Digital Systems

“…It also investigates low-power testing strategies for VLSI circuits, focusing on reducing power consumption during the test phase through test pattern compaction and reordering, demonstrated via the ATALANTA tool and MATLAB. This leads to significant power savings and testing efficiency [15][16].…”

“…Our approach not only meets the basic requirements of BIST, such as fault detection and diagnostic capability, but also reduces power usage significantly for different system sizes (8,16, and 32 bits). The innovative architecture provides scalability, power efficiency, and testing integrity, which is expected to set a new standard for designing future digital systems [6,[12][13][14][15].…”

Built-in generation of weighted test sequences for synchronous sequential circuits

“…Methods to generate weighted pseudo-random patterns for combinational circuits were described in [1]- [15]. One of the methods that can be extended to sequential circuits is the one from [10].…”

“…Methods with extended sets of weights were described in [11] and [15] for the detection of delay faults, that require two-pattern tests. In addi-+ Research supported in part by NSF Grant No.…”

“…In this work, we describe an extension of the 3-weight approach of [10] and the 5-weight approaches of [11] and [15] to synchronous sequential circuits. Under the proposed scheme, a weight is represented by a subsequence α , and implemented by a finite-state machine (FSM) that produces the subsequence α repeatedly.…”