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Importance of delay testing is growing especially for high speed circuits. As delay testing using automatic test equipment is expensive, built-in self-test is an alternative technique that can significantly reduce the cost of delay testing. In this papel; a new test pattem generation method for the detection of delay faults is proposed. It can be seen as a directed random generation technique, and uses some original concepts from Machine Gaming to generate delay fault detecting test pairs. First, (a set of random test vectors is generated. Next, a learning tool working on those vectors provides relevant features of delay fault detecting test pairs. Finally, a set of new test vectors that are consistent with those features is generated. A comparison with other test generation techniques has been done on several circuits, and has shown the eflciency of our solution in terms of test sequence length and delay fault cove rage.

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Based on an incremental path search algorithm, this paper addresses the problem of low power performance driven path classification by sizing selected gates on the shortest and the longest identified paths of the circuit. Delay and power/area constraints are managed using circuit path sizing alternatives defined through a realistic evaluation of gate power and delay. Demonstration of this technique is given on examples of path enumeration and optimization evaluated on several ISCAS '85 benchmarks. Implemented in the POPS tool (Performance Optimization by Path Selection), the accuracy of this technique is compared to evaluation obtained from EPIC tool and SPICE used as a reference.