A new testing method for EEPLA

Diagnosing programmable interconnect systems for FPGAs

“…As in previous papers [4,7], the programmable grid is modeled as follows: it is assumed that the input endpoints are placed at a side (or port) of the programmable grid (initially in the horizontal direction and denoted by the input net set I = I j ; j= 1 ; :::; n as shown in Figure (1)) and the output endpoints are located at a dierent port (initially in the vertical direction and denoted by the output net set O = O j ; j= 1 ; :::; p. Note that in this paper only the case of square grid is considered (i.e. n = p) a s occurring in practice [8,11].…”

“…The walking-1 test set proposed by [2] can avoid the aliasing and confounding problems, All of the above approaches however, can be solely used for diagnosing interconnects in which no programmable device is present. A diagnosis method which partially addresses the issue of programmable chips, has been presented in [7]. This paper introduces a diagnosis method for EEPLAs (electrically erasable programming logic arrays).…”

“…This paper introduces a diagnosis method for EEPLAs (electrically erasable programming logic arrays). However, the approach o f [7] is not applicable to the diagnosis of a FPIS as programmable devices in a FPIS have dierent and more complex programming modes.…”

“…Section (4) has proved that Phase (1) requires 4 tests; so the FPIS of Figure (6) can be tested in 4+4kn 2 tests and the number of programming steps is 4kn+1. Note that the approach o f [7] within the same assumptions and fault models as described in previous sections, requires 5 n 2 k 2 tests and n 2 k 2 programming steps. programmable grids (referred to as switch matrices) to connect g g logic blocks (which are assumed to be not connected to the nets).…”

“…Table (1) compares T t and T p using the proposed method with the number of tests and programming steps required using the test set of [7] for dierent FP-GAs of the XC3000 family. The proposed approach achieves a considerable reduction in the number of tests as well as programming steps, this reduction is more pronounced for the large FPGAs in this family.…”