A new ultra low power high speed dynamic comparator

Rabiei, A; Najafizadeh, Arman; Khalafi, Ali; Ahmadi, S.

doi:10.1109/iraniancee.2015.7146410

Cited by 17 publications

(5 citation statements)

References 7 publications

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“…4. Differential outputs of the passive mixers are then fed into the fully differential inputs of the ultra‐low power comparator consuming only 10 µW [5]. Fig.…”

Section: Simulation Resultsmentioning

confidence: 99%

Ultra‐low power frequency‐shift keying demodulator based on injection‐locking ring oscillator without using phase locked loop for wireless body area networks

Sattari

Safarian

2017

Electron. lett.

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An ultra-low power frequency-shift keying (FSK) demodulator based on injection-locking ring oscillator for wireless body area networks is presented. The proposed system uses the power-efficient injectionlocking ring oscillator (ILRO) to replace the LC oscillator which occupies much more area on chip with higher power consumption. In addition, through the ILRO, the frequency modulated input signal is converted to a full swing rectangular signal, which can be directly demodulated by a chain of down-conversion passive mixers, lowpass filters and a comparator. Power efficiency and simplicity of the proposed structure eliminate conventional FSK demodulator based on power-hungry phase locked loops, which needs to be calibrated by auto-frequency calibrator to periodically compensate the free running frequency deviations due to temperature variations and charge pump leakage current. The proposed FSK demodulator is designed and simulated in 180 nm CMOS technology while consuming only 23.37 µW from a 0.7 V supply.

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“…4. Differential outputs of the passive mixers are then fed into the fully differential inputs of the ultra‐low power comparator consuming only 10 µW [5]. Fig.…”

Section: Simulation Resultsmentioning

confidence: 99%

Ultra‐low power frequency‐shift keying demodulator based on injection‐locking ring oscillator without using phase locked loop for wireless body area networks

Sattari

Safarian

2017

Electron. lett.

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“…It reduces to 250pS at VDD=720mV, temp. =0°C, SS process corner [14][15][16][17][18][19][20][21][22][23][24][25][26]. 790 simulation of maximum worst case condition, the average power consumption of proposed comparator is 77nW which is 87% lower than Paik's comparator and 73% lower than Schinkel's comparator.…”

Section: Functional Simulationmentioning

confidence: 99%

“…However it will reduce the voltage headroom for cascode structure to operate correctly [7][8][9][10][11][12][13][14][15][16][17]. Therefore, to design low voltage and low power dynamic comparator with low supply voltage is a big challenge when the number of transistor stacking is high [16][17][18][19][20][21][22][23].…”

Section: Introductionmentioning

confidence: 99%

Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

Rusli

Shafie

Sidek

et al. 2020

IJEECS

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Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The simulation result show that the proposed comparator circuit achieved significant reduction of power consumption and delay during worst case condition compared to dynamic comparator proposed from previous researchers.

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“…Instead, a dynamic latch comparator is proposed, which consumes well below a milliwatt at low frequencies on the order of 10 MHz [6]. Dynamic latch comparators can have an offset voltage of hundreds of millivolts, so to keep the offset voltage low [7], a Lewis-Gray comparator is used [8]. This has a fair balance between complexity and power consumption.…”

Section: B Receivermentioning

confidence: 99%

Low-Power BPSK Inductive Data Link for an Implanted Intracortical Visual Prosthesis

Omisakin

Mestrom

Bentum

2019

2019 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

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A new ultra low power high speed dynamic comparator

Cited by 17 publications

References 7 publications

Ultra‐low power frequency‐shift keying demodulator based on injection‐locking ring oscillator without using phase locked loop for wireless body area networks

Ultra‐low power frequency‐shift keying demodulator based on injection‐locking ring oscillator without using phase locked loop for wireless body area networks

Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

Low-Power BPSK Inductive Data Link for an Implanted Intracortical Visual Prosthesis

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