A Nine-Level T-Type Packed U-Cell Inverter

Niu, Decun; Gao, Feng; Wang, Panrui; Zhou, Kangjia; Qin, Futian; Ma, Zi

doi:10.1109/tpel.2019.2931523

Cited by 61 publications

(54 citation statements)

References 14 publications

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“…According to Table 3, the proposed SCMLI1 requires a lower number of switches and drivers as compared to the CHB topology and topologies suggested in [14, 17, 20–24]. Also, the proposed SCMLI1 needs a lower number of DC voltage sources as compared to the CHB inverter and topologies of [9–15, 19, 24].…”

Section: Comparison Of the Proposed Scmlis With Other Topologiesmentioning

confidence: 99%

“…To address the above drawbacks, the researchers have been focused on switched‐capacitor MLIs (SCMLIs) [16]. These converters featured a less number of switches and less number of DC power supplies, which contributes to reduced weight, volume, and cost [17]. Two new switched‐capacitor MLIs have been suggested in [18, 19] that benefit from lower switches.…”

Section: Introductionmentioning

confidence: 99%

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A multilevel inverter using switched capacitors with reduced components

Taheri

Rasulkhani

Ren

2020

IET power electron.

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In this study, a novel multi‐source switched‐capacitor converter is proposed. In the proposed topology, the capacitor charging is carried out in a self‐balancing form eliminating the need for additional balancing circuits. After that, the design principle of the proposed inverter is discussed in details. A comparison study between the proposed topology and other existing topologies is provided next. According to this comparison, the proposed topology requires fewer components, such as DC power supplies, switches, capacitors, and diodes. Further, the simulation results for 15‐level and 127‐level and the experimental results for a 15‐level inverter are provided. The simulation and experimental results are in close agreement and verify each other.

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Section: Comparison Of the Proposed Scmlis With Other Topologiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A multilevel inverter using switched capacitors with reduced components

Taheri

Rasulkhani

Ren

2020

IET power electron.

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show abstract

“…With two dc voltage sources and two capacitors, a nine-level output voltage waveform can be achieved, however, the topology lacks the boosting of the input voltage. Similar to [10], nine-level MLI topologies with two dc voltage sources and two capacitors have been proposed in [11], [12]. The authors in [13] proposed two new topologies with two dc voltage source along with two capacitors.…”

Section: Introductionmentioning

confidence: 99%

A Single DC Source Nine-Level Switched-Capacitor Boost Inverter Topology With Reduced Switch Count

et al. 2020

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This paper presents a new boost inverter topology with nine level output voltage waveform using a single dc source and two switched capacitors. The capacitor voltages are self-balancing and thus is devoid of any sensors and auxiliary circuitry. The output voltage is twice higher than the input voltage, which eliminates the need for an input dc boost converter especially when the inverter is powered from a renewable source. The merits of the proposed topology in terms of the number of devices and cost are highlighted by comparing the recent and conventional inverter topologies. In addition to this, the total voltage stress of the proposed topology is lower and have a maximum efficiency of 98.25%. The operation and dynamic performance of the proposed topology have been simulated using PLECS software and are validated using an experimental setup considering a different dynamic operation. INDEX TERMS Multilevel inverter, nine-level inverter, step-up inverter, switched capacitor, reduce switch count.

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“…One class of multilevel inverters has been packed U-cell (PUC) [9][10][11][12][13][14]. In PUC converters, the lack of boosting ability has been the main limitation of these converters for high-voltage applications.…”

Section: Introductionmentioning

confidence: 99%

Dual input switched‐capacitor‐based single‐phase hybrid boost multilevel inverter topology with reduced number of components

Rawa

Siddique

Mekhilef

et al. 2020

IET Power Electronics

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A new switched-capacitor-based topology with features of boosting and self-voltage balancing of the capacitor has been proposed in this study. The proposed multilevel inverter topology uses two isolated dc voltage sources with a switchedcapacitor to produce 11 levels across the load. In this study, two different modes of the selection of dc voltage sources have been discussed for the proposed topology. Furthermore, the generalised structure of the proposed boost topology has also been discussed. Quantitative comparison with several topologies has been carried out to set the benchmark of the proposed topology. Selective harmonic elimination pulse width modulation technique has been adopted to improve the performance of the suggested topology. The power loss analysis of the proposed topology gives the maximum efficiency of 96.5% at the output power of 100 W and has an efficiency value of 95.3% at the output power of 500 W. The proposed topology has been simulated using PLECS and the simulation results have been verifying using an experimental prototype. The proposed topology has been tested for the different types of load and changes in the modulation index. The experimental results have verified the feasibility of the proposed topology.

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A Nine-Level T-Type Packed U-Cell Inverter

Cited by 61 publications

References 14 publications

A multilevel inverter using switched capacitors with reduced components

A multilevel inverter using switched capacitors with reduced components

A Single DC Source Nine-Level Switched-Capacitor Boost Inverter Topology With Reduced Switch Count

Dual input switched‐capacitor‐based single‐phase hybrid boost multilevel inverter topology with reduced number of components

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