A noise-shaping SAR ADC for energy limited applications in 90 nm CMOS technology

Inanlou, Reza; Shahghasemi, Mohsen; Yavari, Mohammad

doi:10.1007/s10470-013-0147-2

Cited by 12 publications

(4 citation statements)

References 26 publications

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“…The ADC core itself is implemented by a binary weighted capacitor array that perform digital to analog conversion (DAC), a comparator and a passive sample-and-hold circuit. The details and considerations of the unit capacitor in the DAC capacitor array as well as the comparator are similar to [7]; but the unit capacitor is 15fF in this design. Also, the arithmetic unit is composed of an 8-bit adder/subtract, an 8bit delay cell and few digital logic gates for control and mode selection.…”

Section: Theoretical Conceptmentioning

confidence: 99%

A Reconfigurable Dual-Mode Tracking SAR ADC without Analog Subtraction

Safarpour

Inanlou

Silvén

et al. 2019

2019 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA)

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In this contribution, it is proposes to limit the quantization search space of a successive approximation analogto-digital converter through an analytic derivation of maximum possible sample-to-sample variation. The presented example design of the proposed ADC is an 8-bit 1MS/s ADC with SAR logic customized to incorporate this priori information while no modification has been required to the analog circuitry. In comparison to conventional SAR conversion, the proposed tracking approach yields significant reduction in total power consumption in oversampling mode. The power savings are due to the reduced number of SAR cycles, and voltage variation minimization across DAC capacitors. The design is reconfigurable both to conventional SAR sampling and the proposed tracking scheme. The approach is attractive for SAR ADCs embedded in very low power micro-controllers.

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Section: Theoretical Conceptmentioning

confidence: 99%

A Reconfigurable Dual-Mode Tracking SAR ADC without Analog Subtraction

Safarpour

Inanlou

Silvén

et al. 2019

2019 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA)

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“…Binary-weighted capacitive [23] array DAC with attenuation capacitor is employed to convert the digital numbers of the SAR logic to analog signal, with minor modification for dual mode operation. The details and considerations of the unit capacitor in the DAC capacitor array as well as the SAR logic are similar to [24]. Fig.…”

Section: B Hardware Design and Simulationmentioning

confidence: 99%

ADC-Assisted Random Sampler Architecture for Efficient Sparse Signal Acquisition

Safarpour

Inanlou

Charmi

et al. 2018

IEEE Trans. VLSI Syst.

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“…The proposed self-dithering ADC is similar to the wellknown noise-shaping architecture [22]- [25] except that the feedback loop is opamp-free and the contribution of the LSB segment is later removed using digital subtraction. A possible implementation of the DAC in self-dithering scheme is given in Fig.2(b), where the coarse sub-DAC, the fine sub-DAC and the feedback sub-DAC are separate binary arrays of capacitors.…”

Section: B Self-dithering Technique and Error Analysismentioning

confidence: 99%

Self-Dithering Technique for High-Resolution SAR ADC Design

Jin

Yang

et al. 2015

IEEE Trans. Circuits Syst. II

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In this brief, a high-resolution SAR ADC architecture for biomedical data acquisition is proposed. Filtered LSB segment is employed as a dither to improve the resolution. Theoretical analysis and behavioral simulation show that the error of the MSB segment can be converted into a shaped noise, if the input signal is sufficiently small. The proposed self-dithering technique can be used together with averaging to improve the SNR and the DNL performance. The performance improvement is similar to that of a conventional nonsubtractive scheme using a uniform deterministic dither, but with simplified hardware and reduced computation complexity.

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A noise-shaping SAR ADC for energy limited applications in 90 nm CMOS technology

Cited by 12 publications

References 26 publications

A Reconfigurable Dual-Mode Tracking SAR ADC without Analog Subtraction

A Reconfigurable Dual-Mode Tracking SAR ADC without Analog Subtraction

ADC-Assisted Random Sampler Architecture for Efficient Sparse Signal Acquisition

Self-Dithering Technique for High-Resolution SAR ADC Design

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