A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation

Huang, Hai; Xu, Hongda; Elies, Brian; Chiu, Yun

doi:10.1109/jssc.2017.2732731

Cited by 72 publications

(28 citation statements)

References 23 publications

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“…It reduces to 250pS at VDD=720mV, temp. =0°C, SS process corner [14][15][16][17][18][19][20][21][22][23][24][25][26]. 790 simulation of maximum worst case condition, the average power consumption of proposed comparator is 77nW which is 87% lower than Paik's comparator and 73% lower than Schinkel's comparator.…”

Section: Functional Simulationmentioning

confidence: 99%

“…To ensure the robustness of a design, process corner simulation is required at the design stage. Process corner represents the extremes parameter variation of integrated circuit design which is fabricated on semiconductor wafer [6][7][8][9][10][11][12][13][14][15]. Parameter variations include range of process transistor properties, supply voltages and die temperatures [8,9].…”

Section: Introductionmentioning

confidence: 99%

“…In nanoscale technology, scaling down of voltage supply near to threshold voltage can provide excessive savings in dynamic energy. However it will reduce the voltage headroom for cascode structure to operate correctly [7][8][9][10][11][12][13][14][15][16][17]. Therefore, to design low voltage and low power dynamic comparator with low supply voltage is a big challenge when the number of transistor stacking is high [16][17][18][19][20][21][22][23].…”

Section: Introductionmentioning

confidence: 99%

“…The most popular energy efficient comparator is dynamic comparator Figure 1 which only operates during regeneration time [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. The additional features are high input impedance, rail to rail output swing, zero static power, low offset voltage and fast decision making that comes from strong positive feedback and .…”

Section: Introductionmentioning

confidence: 99%

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Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

Rusli

Shafie

Sidek

et al. 2020

IJEECS

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Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The simulation result show that the proposed comparator circuit achieved significant reduction of power consumption and delay during worst case condition compared to dynamic comparator proposed from previous researchers.

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Section: Functional Simulationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

Rusli

Shafie

Sidek

et al. 2020

IJEECS

View full text Add to dashboard Cite

show abstract

“…A major design bottleneck is that the compromise between faster settling speed and power consumption reduction. Numerous ways to either enhance the class AB operation of the OTA or to make its bias current signal time-dependent can be found in the literature [1][2][3][4][5][6]. Dominantly they affect the internal design and dimensioning of the OTA itself.…”

Section: Introductionmentioning

confidence: 99%

Continuously controlled and discrete-level charge pumping techniques implemented in SC integrators

Sun

Rahkonen

2019

Analog Integr Circ Sig Process

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This paper presents two methods to reduce power consumption of switched capacitor (SC) integrators in sigma-delta analog to digital converters. The proposed two methods are based on the passive charge redistribution technique, injecting charge into the output of the first integrator. The injected charge can be attained by a continuous function of the input voltage and feedback, or by quantizing the injected charge into three levels. In both cases, the main purpose is to minimize the initial transient voltage at the input of the first operational transconductance amplifiers (OTA), in order to bypass the slewing region of the OTA and enter into the linear settling region. Then a minor charge is left, and needs to be moved by the OTA. Using these two charge pumping techniques separately, a 10-bit performance of a conventional second-order delayed cascaded 1-bit sigma-delta modulator which consists of two SC integrators can be obtained by only consuming 60% power dissipation of the traditional structure without proposed techniques.

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Analysis and Design of an Efficient 8-Bit 2b/Cycle SAR ADC with Multiple Calibration Techniques

Chen

Yuan

Tang

et al. 2022

Circuits Syst Signal Process

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A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation

Cited by 72 publications

References 23 publications

Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

Continuously controlled and discrete-level charge pumping techniques implemented in SC integrators

Analysis and Design of an Efficient 8-Bit 2b/Cycle SAR ADC with Multiple Calibration Techniques

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