A non-scan DFT method at register-transfer level to achieve complete fault efficiency

Abstract

-This paper presents a non-scan design-fortestability (DFT) method for VLSIs designed at registertransfer level (RTL) to achieve complete fault efficiency. In RTL design, a VLSI generally consists of a controller and a data path. The controller and the data path are connected with internal signals: control signals and status signals. The proposed method consists of the following two steps. First, we apply our DFT methods [1] and [2, 3] to the controller and the data path, respectively. Then, to support at-speed testing, we append a test plan generator which generates a sequence of test control vectors for the modified data path. Our experimental results show that the proposed method can reduce significantly both of test generation time and test application time compared with the full-scan design, though the hardware overhead of our method is slightly larger than that of the full-scan design.

A nonscan DFT method for RTL circuits based on fixed‐control testability

“…9, and we will show that the area overheads of the test plan generation circuit and the entire circuit can be reduced compared to Ref. 9.…”

“…In the experiments, we will show that the proposed method is equal to the test generation time and test execution time of Ref. 9. The area overhead of the data path is equal to that of Ref.…”

“…1), the design for testability is performed for the controller and the data path, respectively, similar to the method of Ref. 9. For the controller, the method of Ref.…”

“…To remedy these problems, test generation and design for testability methods dealing with controller/data path circuits at register transfer (RT) level have been proposed in recent years [4,5,[7][8][9]. The controllers at RT level are described in a state transition diagram and the data paths are described by the circuit elements such as operational modules composed of registers and combinational circuits, and the signal lines connecting these circuit elements.…”

“…The nonscan design for testability for the entire controller/data path circuits includes a method [9] in which the method of Ref. 7 and the strongly testable design for testability [8] are applied for the respective controllers and data paths.…”