This paper presents a non-scan design-fortestability (DFT) method for VLSIs designed at registertransfer level (RTL) to achieve complete fault efficiency. In RTL design, a VLSI generally consists of a controller and a data path. The controller and the data path are connected with internal signals: control signals and status signals. The proposed method consists of the following two steps. First, we apply our DFT methods [l] and [2, 31 to the controller and the data path, respectively. Then, to support at-speed testing, we append a test plan generator which generates a sequence of test control vectors for the modified data path. Our experimental results show that the proposed method can reduce significantly both of test generation time and test application time compared with the full-scan design, though the hardware overhead of our method is slightly larger than that of the full-scan design.

This paper presents a non-scan designfor-testability method for controllers that are synthesized from FSMs (Finite State Machines). The proposed method can achieve complete fault eficiency: test patterns for a combinational circuit of a controller are applied to the controller using state transitions of the FSM. In the proposed method, at-speed test application can be performed and the test application time is shorter than previous methods. Moreover, experimental results show the urea overhead is low.

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-This paper presents a non-scan design-fortestability (DFT) method for VLSIs designed at registertransfer level (RTL) to achieve complete fault efficiency. In RTL design, a VLSI generally consists of a controller and a data path. The controller and the data path are connected with internal signals: control signals and status signals. The proposed method consists of the following two steps. First, we apply our DFT methods [1] and [2, 3] to the controller and the data path, respectively. Then, to support at-speed testing, we append a test plan generator which generates a sequence of test control vectors for the modified data path. Our experimental results show that the proposed method can reduce significantly both of test generation time and test application time compared with the full-scan design, though the hardware overhead of our method is slightly larger than that of the full-scan design.

If, upon substituting signal lines for all flip‐flops in a sequential circuit, the test generation problem for this sequential circuit can be reduced to the problem of test generation for a combinational circuit, one may call this sequential circuit a sequential circuit allowing test generation with combinational test generation complexity. For example, balanced structures are characterized by this feature. The authors introduce a new wider class called internally balanced structures. The sequential circuits can be classified by the circuit structure as follows: {sequential circuits of acyclic structure} ⊃ {sequential circuits of internally balanced structure} ⊃ {sequential circuits of balanced structure}. It is shown that, as opposed to sequential circuits of acyclic structure, which do not necessarily allow test generations with combinational test generation complexity, sequential circuits of internally balanced structure and balanced structure allow test generation with combinational test generation complexity. On the other hand, it is shown that finite state machines (FSM) can be grouped by their realization possibility as follows: {FSM allowing realization as acyclic structure} = {FSM allowing realization as internally balanced structure} ⊃ {FSM allowing realization as balanced structure}. Finally, the authors discuss using features of the internally balanced structures which allow test generation with combinational test generation complexity for implementing designs for testability based on the new partial scan approach, and for reducing the test generation time in sequential circuits. © 1998 Scripta Technica, Syst Comp Jpn, 28(11): 11–21, 1997