A non-scan DFT method at register-transfer level to achieve complete fault efficiency

Abstract

This paper presents a non-scan design-fortestability (DFT) method for VLSIs designed at registertransfer level (RTL) to achieve complete fault efficiency. In RTL design, a VLSI generally consists of a controller and a data path. The controller and the data path are connected with internal signals: control signals and status signals. The proposed method consists of the following two steps. First, we apply our DFT methods [l] and [2, 31 to the controller and the data path, respectively. Then, to support at-speed testing, we append a test plan generator which generates a sequence of test control vectors for the modified data path. Our experimental results show that the proposed method can reduce significantly both of test generation time and test application time compared with the full-scan design, though the hardware overhead of our method is slightly larger than that of the full-scan design.

A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint

“…Since the pseudo primary inputs (PPI), which are the outputs of the status registers, are observable in this figure, the PPIs connect with the primary output. Thus, multiplexers are added on the PPI and are connected to the primary outputs of the data path in order to reduce the overhead of primary output pins [11]. Here, PI, PO, SR, PPI, PPO, and R denote the primary inputs, primary outputs, status registers, pseudo primary inputs (outputs of the status registers), pseudo primary outputs (inputs of the status registers), and a reset input, respectively.…”

“…The FSM has both a completely specified FSM [14], in which the next state and the output are specified for all of the inputs of each state, and an incompletely specified FSM [11], in which the next state and the output are not specified for all of the inputs of each state. In this paper, state transitions in the incompletely specified FSMs that are not specified are assumed to be the same as either of the state transitions that are specified.…”

A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability

“…We also propose a DFT method for data paths which makes a data path fixed-control testable and a test architecture for a whole circuit consisting of both a controller and a data path. Experimental results using some benchmark circuits show that the method proposed in this paper can reduce hardware overhead compared to that in [3].…”

“…However, if we consider a DFT method for the whole circuit consisting of both a controller and a data path, we have to remove this assumption by adding some extra logic to provide both controllability and observability of those control and status signals. In our previous work [3], we resolved this problem by (1) adding multiplexers on those control and status signals to connect directly from primary inputs and to primary outputs and (2) embedding an extra circuit in the controller side, called a test plan generator, which can generate test plans for the data path of an RTL circuit, where a test plan is a control sequence to propagate 1 Fault efficiency is the ratio of the number of faults detected and proved redundant to the total number of faults. test patterns for a combinational hardware element from the primary inputs to the inputs of the hardware element and to propagate responses from the output of the hardware element to the primary outputs.…”

“…A controller and a data path are interconnected by internal signals: control signals and status signals. In our previous work [3], we proposed a DFT method for an RTL circuit which consists of a controller part and a data path part. The DFT method integrates the DFT method of [4] for controllers and that of [5] for data paths.…”