False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults

Yoshikawa, Yasuhiro; Ohtake, Satoshi; Fujiwara, Hideo

doi:10.1109/ats.2007.70

Cited by 8 publications

(20 citation statements)

References 13 publications

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“…In this section, we show experimental results for evaluating our RTL path mapping method by mapping RTL paths and RTL false paths identified with the method proposed in [7]. We used three RTL benchmark circuits, LWF, Tseng and Paulin and an industrial circuit, MPEG.…”

Section: Resultsmentioning

confidence: 99%

“…If we can remove the assumption of logic synthesis, we can utilize the identification method reported in [7] for more general circuits synthesized without the restriction. Therefore, we obtain the following theorem.…”

Section: Rtl False Path Mappingmentioning

confidence: 99%

“…While not specifically targeting false paths, Nourani et al [6] proposed a method using timing analysis and RTL design information to determine the actual critical path and avoid false paths longer than the true critical path. Yoshikawa et al [7], [8] defined RTL false paths and proposed a method to identify them. However, these methods are useful only if the correspondence between paths at RTL and paths at gate level can be established.…”

Section: Introductionmentioning

confidence: 99%

“…However, these methods are useful only if the correspondence between paths at RTL and paths at gate level can be established. Until now, the correspondence has been established through module interface preserving-logic synthesis (MIP-LS) [7]. Currently, using MIP-LS is the only way to guarantee information on the correspondence.…”

Section: Introductionmentioning

confidence: 99%

“…The defini-tion of RTL false path in [7] assumes MIP-LS and the assumption guarantees that the corresponding gate level paths are false. In this paper, we show that any corresponding gate level path mapped from the set of RTL false paths by using the proposed method with an arbitrary logic synthesis is false.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification

Iwata

Ohtake

Fujiwara

2010

IEICE Trans. Inf. & Syst.

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SUMMARYInformation on false paths in a circuit is useful for design and testing. The use of this information may contribute not only to reducing circuit area, the time required for logic synthesis, test generation and test application of the circuit, but also to alleviating over-testing. Since identification of the false paths at gate level is hard, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and at gate level can be established. Until now, giving restriction on logic synthesis is the only way to establish the correspondence. However, it is not practical for industrial designs. In this paper, we propose a method for mapping RTL false paths to their corresponding gate level paths without such a specific logic synthesis; it guarantees that the corresponding gate level paths are false. Experimental results show that our path mapping method can establish the correspondences of RTL false paths and many gate level false paths. key words: false path, high level testing, path mapping, functional equivalence

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Section: Resultsmentioning

confidence: 99%

Section: Rtl False Path Mappingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification

Iwata

Ohtake

Fujiwara

2010

IEICE Trans. Inf. & Syst.

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Fast false path identification based on functional unsensitizability using RTL information

Yoshikawa¹,

Ohtake²,

Inoue³

et al. 2009

2009 Asia and South Pacific Design Automation Conference

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Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths

Yoneda

Ohtake

et al. 2008

2008 17th Asian Test Symposium

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As LSI manufacturing technology improves and the time-tomarket for products becomes stricter, more and more circuit designs have multiple clock domains due to concerns such as design re-use, power reduction and temperature control. It is not uncommon for these designs to have multi-cycle paths which are untestable. The rapid identification of these untestable paths reduces test generation time as well as over-testing due to design for testability (DFT). For current and future designs, this has already become impractical at the gate-level. This paper presents a method to identify nonrobust untestable multi-cycle paths at the register transfer level (RTL) and the details in a case study of a benchmark circuit.

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False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults

Cited by 8 publications

References 13 publications

A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification

A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification

Fast false path identification based on functional unsensitizability using RTL information

Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths

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