A nonredundant ternary CAM circuit for network search engines

Akhbarizadeh, M.J.; Nourani, Mehrdad; Vijayasarathi, D.S.; Balsara, T.

doi:10.1109/tvlsi.2006.871760

Cited by 16 publications

(10 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…They are expensive, power-hungry, and offer little adaptability to new addressing and routing protocols [7]. As shown in Table 1, SRAMs outperform TCAMs with respect to speed, density, and power consumption [2,3,4,5,6].…”

Section: Internet Protocol Packet Forwardingmentioning

confidence: 99%

Scalable High Throughput and Power Efficient IP-Lookup on FPGA

Prasanna

2009

2009 17th IEEE Symposium on Field Programmable Custom Computing Machines

View full text Add to dashboard Cite

Section: Internet Protocol Packet Forwardingmentioning

confidence: 99%

Scalable High Throughput and Power Efficient IP-Lookup on FPGA

Prasanna

2009

2009 17th IEEE Symposium on Field Programmable Custom Computing Machines

View full text Add to dashboard Cite

“…Hayashi et al describe a CAM-based design that utilizes CAM units that can have only one global mask register [10]. Akhbarizadeh et al encoded the mask bit in the address for each 8-bit block using only nine SRAM cells [11]. This circuit utilized a more complicated match line structure, but still requires masking multiple entries to find the longest match.…”

Section: Hardware Ip Lookupmentioning

confidence: 99%

Low power fast and dense longest prefix match content addressable memory for IP routers

Maurya

Clark

2009

Proceedings of the 2009 ACM/IEEE International Symposium on Low Power Electronics and Design

View full text Add to dashboard Cite

An IP router determines the next hop for an internet protocol packet by finding the longest prefix match. Ternary CAMs, which allow bit masking of the IP address, are commonly used for this fast search function. In this paper, a CAM that directly determines the longest prefix match to the stored address is described. One of these best matching (IPCAM) entries replaces on average 22 TCAM entries. Overall, the resulting IPCAM array is less than 1/10 the size of the equivalent TCAM and dissipates 93.5% less dynamic power. The design automatically produces an encoded prefix match length that is limited by the prefix mask, so entries do not need to be sorted in prefix mask length order. Simulations of extracted layouts in a bulk CMOS 65-nm foundry process show the proposed IPCAM circuits can operate above 1 GHz

show abstract

“…TCAM is the most expensive and power-hungry component in routers and switches. It requires 2.7 times more transistors per bit [11] and consumes an order of magnitude more power [35] compared with the same size of SRAM. Therefore, increased address length imposes substantial cost and power consumption in particular on high-speed border routers with TCAM.…”

Section: Introductionmentioning

confidence: 99%

Caesar: high-speed and memory-efficient forwarding engine for future internet architecture

Moradi¹,

Qian²,

Xu³

et al. 2015

2015 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS)

View full text Add to dashboard Cite

In response to the critical challenges of the current Internet architecture and its protocols, a set of so-called clean slate designs has been proposed. Common among them is an addressing scheme that separates location and identity with self-certifying, flat and non-aggregatable address components. Each component is long, reaching a few kilobits, and would consume an amount of fast memory in data plane devices (e.g., routers) that is far beyond existing capacities. To address this challenge, we present Caesar, a high-speed and length-agnostic forwarding engine for future border routers, performing most of the lookups within three fast memory accesses.To compress forwarding states, Caesar constructs scalable and reliable Bloom filters in Ternary Content Addressable Memory (TCAM). To guarantee correctness, Caesar detects false positives at high speed and develops a blacklisting approach to handling them. In addition, we optimize our design by introducing a hashing scheme that reduces the number of hash computations from k to log(k) per lookup based on hash coding theory. We handle routing updates while keeping filters highly utilized in address removals. We perform extensive analysis and simulations using real tra c and routing traces to demonstrate the benefits of our design. Our evaluation shows that Caesar is more energy-e cient and less expensive (in terms of total cost) compared to optimized IPv6 TCAM-based solutions by up to 67% and 43% respectively. In addition, the total cost of our design is approximately the same for various address lengths.

show abstract

A nonredundant ternary CAM circuit for network search engines

Cited by 16 publications

References 25 publications

Scalable High Throughput and Power Efficient IP-Lookup on FPGA

Scalable High Throughput and Power Efficient IP-Lookup on FPGA

Low power fast and dense longest prefix match content addressable memory for IP routers

Caesar: high-speed and memory-efficient forwarding engine for future internet architecture

Contact Info

Product

Resources

About