Abstract-Conventional routing cache systems store destination IP addresses in their cache directory. We present a routing cache technique that stores the most recently used route prefixes, instead of IP addresses, to achieve significantly smaller cache size. A nesting prefix is partially represented in this cache by its minimal expansions. Such expanded prefixes are obtained using an incremental technique without any modifications to the routing table. Consequently, our cache works with most of the common route lookup algorithms and efficiently maintains coherency with the routing table. Experiments show that for a hit ratio over 0.96 our design can achieve more than 33 times reduction in cache size, compared to a conventional routing cache.

Abstract-In this paper, we present an efficient IP packet forwarding methodology and architecture. This is achieved by partitioning the lookup table into the smaller ones for each output port and allowing a forwarding engine to process them in parallel. This effectively reduces the complexity of finding "the longest prefix match" problem to "the first prefix match" problem.

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An optimized Ternary CAM concept is introduced for the hardware search engines in high-speed Internet routers. Our design employs + 1 RAM bits to store a word of size , whereas a conventional TCAM needs 2 RAM bits for the same word size. Based on this concept an 8-bit cluster is designed out of 9 SRAM bits, used as the basic building block of our Prefix-CAM (PCAM) structure. Four such clusters merge to store a 32-bit IPv4 prefix, thus, configuring a PCAM suitable for Internet packet forwarding. This PCAM module employs 48% less SRAM cells and a total of 22% less transistors plus 50% less address decode interconnects compared to a conventional TCAM, for equal storage size and equal functionality. We show that PCAM can be employed for multifield packet classification. Other factors, such as lookup speed and power dissipation, are not adversely affected.Index Terms-Forwarding engine, packet classification, prefix-CAM, route lookup table, ternary content addressable memory.

Abstract-An optimized Ternary CAM concept is introduced for application in the longest prefix matching tasks of the Internet search engines. It employs w · 1 RAM bits for a word of size w.A conventional TCAM needs 2w RAM bits for the same word size. Based on this concept an 8 bit Prefix-CAM cluster is designed out of 9 SRAM bits, four of which merge to store a 32-bit IPv4 prefix. A complete Prefix-CAM module employs 22% less transistors than a conventional TCAM, for equal storage size and equal functionality. We confirm the 22% area saving by implementing the layouts for Prefix-CAM and TCAM words. Our design also reduces interconnect area by reducing address decode lines.