A Novel 4H-SiC Super Junction UMOSFET with Hetero-Junction Diode for Enhanced Reverse Recovery Characteristics and Low Switching Loss

Kim, J.; Kim, K.

doi:10.1134/s1063782620050061

Cited by 2 publications

(2 citation statements)

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“…With charge-balanced npillar and p-pillar, the super-junction (SJ) MOSFET has more superior electrical characteristics compared with conventional SiC trench MOSFET. [16][17][18][19][20] Vudumula et al [16] studied the static and dynamic characteristics of the CoolSiC trench MOS-FET structure by introducing the concept of super-junction, and the structure provides a good trade-off between gate oxide reliability and R on,sp . Orouji et al [17] proposed to replace the p+ shield region with an n-type pillar and a p-type pillar at the bottom of the gate trench.…”

Section: Introductionmentioning

confidence: 99%

“…Deng et al [18] studied a novel structure embedded in a floating p-column in the drift region, which ensures that the V BR is not reduced, allowing for a compromise between the R on,sp , and the short-circuit characteristics. Kim [19] proposed a novel SJ structure with a hetero-junction diode for improved reverse recovery characteristics and switching energy loss. He et al [20] investigated a new SJ structure by using grounded p+ buried layers and connected p columns to encapsulate deep trench gate oxide to reduce the saturation current.…”

Section: Introductionmentioning

confidence: 99%

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A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

2022

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In this article, an optimized silicon carbide (SiC) trench Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) structure with side-wall p-type pillar (p-pillar) and wrap n-type pillar (n-pillar) in the n-drain was investigated utilizing Silvaco TCAD simulations. The optimized structure main includes a p+ buried region, a light n-type current spreading layer (CSL), a p-type pillar region, and a wrapping n-type pillar region at the right and bottom of the p-pillar. The improved structure is named SNPPT-MOS. The side-wall p-pillar region could better relieve the high electric field around the p+ shielding region and the gate oxide in the off-state mode. The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance (R on,sp). As a result, the SNPPT-MOS structure exhibits that a higher figure of merit (FoM) related to the breakdown voltage (V BR) and the R on,sp (V BR 2/R on,sp) of the SNPPT-MOS is improved by 44.5%, respectively, with comparison to that of the conventional trench gate SJ MOSFET (full-SJ-MOS). In addition, the SNPPT-MOS structure achieves a much faster-switching speed than the full-SJ-MOS, and the result indicated an appreciable reduction in the switching energy loss.

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