A novel 80V-class HV-MOS platform technology featuring high-side capable 30V-gate-voltage drift-NMOSFET and a trigger controllable ESD protection BJT

This paper discusses a circuit simulation model for interdigitated source LDMOS. As p+ well contacts are inserted to the source regions, the device achieves high breakdown immunity without using high voltage p+ implantation under the source. However, since the parasitic resistance near the source p+ region is not formulated in the conventional compact model, the accuracy of the model is an issue. To solve this problem, this paper proposes a macro model, in which parasitic resistance near the p+ region is represented by an effective resistance (Rs). The formulation of Rs is discussed and the feasibility of the model is demonstrated.

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A novel 80V-class HV-MOS platform technology featuring high-side capable 30V-gate-voltage drift-NMOSFET and a trigger controllable ESD protection BJT

Cited by 2 publications

References 8 publications

Design of an 80V-class high-side capable double-resurf JI L-IGBT

Design of an 80V-class high-side capable double-resurf JI L-IGBT

Accurate spice modeling of 80V power LDMOS with interdigitated source structure

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