The number of the dummy via can significantly affect the interconnect average temperature. This paper explores the modeling of the interconnect average temperature in the presence of multiple dummy vias. The proposed model incorporates the multi-via effect into the effective thermal conductivity of the interlayer dielectric (ILD) to obtain accurate results. Using different ILDs, the multi-via effect is analyzed and discussed. Also, the extended applications of the multi-via effect are presented in this paper to obtain the minimum interconnect average temperature increase with a given via separation or number. This study suggests that the multi-via effect should be accounted for in integrated circuits design to optimize the performance and design accuracy of integrated circuits. As feature sizes have decreased, a continuous increase in integration density has resulted in higher overall chip temperature, which makes power dissipation and thermal issues a major impediment in the design of ultra large scale integrated circuits (ULSI) [1][2][3]. Research has shown that on-chip global interconnect self-heating contributes about 34% of the total chip power dissipation in an Intel microprocessor with 130-nm features [4]. Moreover, because of the reduction of the distance between the substrate and the top-most metal layers [5], the substrate temperature variations have an increased effect on interconnect temperature profile. In high-performance integrated circuits (ICs), the peak chip temperature can reach 210°C and the thermal gradients can rise above 50°C when in the GHz frequency regime [6,7]. The temperature distribution can strongly affect the interconnect resistance, and, consequently, the signal integrity of circuits can be degraded. Furthermore, low-k materials are generally used to reduce the effect on interconnect time delay, crosstalk and dynamic power consumption [8,9]. However, because of the poor thermal conductivity of such materials, most of the *Corresponding author (email: fire5water@hotmail.com) Joule heating produced by the interconnects on every level cannot be transmitted to the heat sink. Therefore it accumulates which leads to a larger interconnect temperature rise. However, vias can effectively reduce interconnect temperature increase. Hence the interconnect temperature will not be not as high would be estimated or the previous circumstance [10][11][12][13]. Because of the reasonable thermal conductivity of vias, dummy vias can be introduced to reduce the interconnect temperature in IC design. A dummy via is a kind of via which that used to conduct heat but is not electrically connected [12][13][14][15]. The interconnect temperature profile can be strongly affected by the presence of dummy vias. Over-estimation of the interconnect temperature can lead to design failure or unnecessarily conservative design. Therefore, an accurate prediction of interconnect temperature is a necessary precondition for interconnect characterization.
