With the integrated circuits processing stepping into nanometer scale, the interconnect Joule heat becomes significantly large. Based on the RLC π equivalent circuit, this paper proposes a novel accurate model to evaluate Joule heat power of interconnected line in VLSI. The shielding effect of the inductor and the non-ideal step stimulation are considered in the proposed model. The power consumption of a typical interconnected topology in 90 nm complementary metal-oxide semiconductor process is computed. The error between results of this proposed method and Hspice simulation is within 3% when the input signal’s delay time is within 1 ns. The proposed model can be used to estimate Joule heat consumption where rough heat control is needed, such as route structure in the network on chip.

Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing and adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor (CMOS) interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.

An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering * Zhu Zhang-Ming(朱樟明) a)b) † , Hao Bao-Tian(郝报田) a) , En Yun-Fei(恩云飞) a)b) , Yang Yin-Tang(杨银堂) a) , and Li Yue-Jin(李跃进) a)

Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65 nm complementary metal oxide semiconductor (CMOS) process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design (CAD) of very large-scale integrated circuits (VLSIs) in nano-scale technologies.

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