A novel low-swing interconnect optimization model with delay and bandwidth constraints

Self Cite

Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit (3D IC) is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip (SOC) is established by evaluating the constraints of 1) wiring resource, 2) wiring bandwidth, and 3) wiring noise. In comparison to a two-dimensional integrated circuit (2D IC) in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.

Section: Wiring Noisementioning

confidence: 99%

Three-dimensional global interconnect based on a design window

Qian¹,

Zhu²,

Yang³

2011

Self Cite

“…[6][7][8][9] The very large scale integrated circuit (VLSI) is sensitive to defects in the IC manufacturing process, and the rate of the IC yield loss which is caused by defects in the manufacturing process is more than 80%. [10] The important approach to raising IC yield related to random defects is to optimize the IC layout in the IC design stage, especially in the layout design stage, which depends on the information about the random defects causing yield loss. [11][12][13][14] The existing experimental results show that the real defects are of irregular shape, [15][16][17][18] and that these defects have a certain space distribution.…”

Section: Introductionmentioning

confidence: 99%

Open critical area model and extraction algorithm based on the net flow-axis

Wang

Gao

et al. 2013

In the integrated circuit manufacturing process, the critical area extraction is a bottleneck to the layout optimization and the integrated circuit yield estimation. In this paper, we study the problem that the missing material defects may result in the open circuit fault. Combining the mathematical morphology theory, we present a new computation model and a novel extraction algorithm for the open critical area based on the net flow-axis. Firstly, we find the net flow-axis for different nets. Then, the net flow-edges based on the net flow-axis are obtained. Finally, we can extract the open critical area by the mathematical morphology. Compared with the existing methods, the nets need not to divide into the horizontal nets and the vertical nets, and the experimental results show that our model and algorithm can accurately extract the size of the open critical area and obtain the location information of the open circuit critical area.

“…[5] As we know, the impact of interconnects is more important than that of gates. [6,7] The RC delay of interconnects is 2.75 times larger than the gate delay at 90 nm; 4.29 times larger at 65 nm, and 7.56 times larger at 45 nm. [8] Interconnect process variation has a direct impact on the delay of interconnect tree.…”

Section: Introductionmentioning

confidence: 99%

Statistical Elmore delay of RC interconnect tree

Dong¹,

Yang²,

Chai³

et al. 2010

As feature size keeps scaling down, process variations can dramatically reduce the accuracy in the estimation of interconnect performance. This paper proposes a statistical Elmore delay model for RC interconnect tree in the presence of process variations. The suggested method translates the process variations into parasitic parameter extraction and statistical Elmore delay evaluation. Analytical expressions of mean and standard deviation of interconnect delay can be obtained in a given fluctuation range of interconnect geometric parameters. Experimental results demonstrate that the approach matches well with Monte Carlo simulations. The errors of proposed mean and standard deviation are less than 1% and 7%, respectively. Simulations prove that our model is efficient and accurate.