An accurate Joule heat model of RLC interconnect based on π equivalent circuit

Abstract

With the integrated circuits processing stepping into nanometer scale, the interconnect Joule heat becomes significantly large. Based on the RLC π equivalent circuit, this paper proposes a novel accurate model to evaluate Joule heat power of interconnected line in VLSI. The shielding effect of the inductor and the non-ideal step stimulation are considered in the proposed model. The power consumption of a typical interconnected topology in 90 nm complementary metal-oxide semiconductor process is computed. The error between results of this proposed method and Hspice simulation is within 3% when the input signal’s delay time is within 1 ns. The proposed model can be used to estimate Joule heat consumption where rough heat control is needed, such as route structure in the network on chip.

An RLC interconnect analyzable crosstalk model considering self-heating effect

“…In this paper, we use the second-order Pade' model which is stable and efficient in computation, [5] then v 2n (s) is described as…”

“…Using the Kirchhoff's current law (KCL) and the Kirchhoff's voltage law (KVL) to analyse each RLC subsection in Fig. 6, we can obtain the following matrix formula: [5,8]…”

“…where U (t) represents the step signal, V DD the amplitude of the voltage and t r the rise (fall) time of the ramp input. It is easy to find that using the initial and the final value theorems of the Laplace domain, we can expand v 1 (s) and v 2 (s) into the following series: [5,8]…”

“…However, in these studies the influences of the temperature distribution effect on interconnect crosstalk were not considered. As the CMOS integrated circuits develop into nanometer level, the influence of inductive coupling effect strengthens gradually and interconnect analytical crosstalk model also develops from the RC model to a more accurate RLC model, [5,6,8] but in these models the aggressive influence of interconnect self-heating effect on the RLC crosstalk is not taken into consideration.…”

“…In this paper, we analyse the temperature distribution of multilevel interconnect based on the interconnect parameter of the 65-nm CMOS process, propose a kind of multilevel interconnect temperature distribution model, then, use the analytical RLC crosstalk model in Ref. [5] to develop a kind of analytical RLC crosstalk model with considering thermal profile, which is verified based on the intermediate and global interconnect of the 65-nm CMOS process and carry on the analysis and discussion on the results.…”