2016 International Conference on ReConFigurable Computing and FPGAs (ReConFig) 2016
DOI: 10.1109/reconfig.2016.7857146
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A novel and efficient method to initialize FPGA embedded memory content in asymptotically constant time

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Cited by 2 publications
(14 citation statements)
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“…The time (latency) required for transferring the processed data to/from input/output buffers has the same lower bound asymptotic complexity as the compression itself, the Ω(n). The question is, which compression dictionary architecture can match or decrease such lower bound asymptotic complexity, especially when the required dictionary can be larger than the buffers [5]?…”
Section: Discussionmentioning
confidence: 99%
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“…The time (latency) required for transferring the processed data to/from input/output buffers has the same lower bound asymptotic complexity as the compression itself, the Ω(n). The question is, which compression dictionary architecture can match or decrease such lower bound asymptotic complexity, especially when the required dictionary can be larger than the buffers [5]?…”
Section: Discussionmentioning
confidence: 99%
“…On the other hand, no current architecture has emphasized lowering an architecture overhead to reduce the respective architecture computation latency or resource utilization. It has been identified [5] that the overhead (a compression dictionary initialization) necessary for the compression process (computation phase) could require more time than the compression itself.…”
Section: Brief Motivation and Contributionsmentioning
confidence: 99%
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