A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations

Fathi, Amir; Azizian, Sarkis; Hadidi, Khayrollah; Khoei, Abdollah

doi:10.1587/transele.e95.c.710

Cited by 13 publications

(17 citation statements)

References 2 publications

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“…Different designs and architectures for 4-to-2 compressor circuits presented in literature [13][14][15][16][17][18][19][20][21][22]. A 4-to-2 compressor can be constructed using two 3-to-2 compressors (full adders) in series, shown in Figure 1.…”

Section: Related Workmentioning

confidence: 99%

A New High Speed Carbon Nanotube Field Effect Transistor-Based Structure for 4-to-2 Compressor Cell

Bagherizadeh

Eshghi

2016

j comput theor nanosci

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This paper presents a high speed design of 4-to-2 compressor, using Carbon Nanotube Field Effect Transistor (CNFET). CNFET is very suitable for low-voltage and high-frequency applications. Several conventional and state-of-the-art 4-to-2 compressor cells are also surveyed and compared in this paper. All designs are simulated by HSPICE with 32 nm CNFET technology. These designs have also been simulated at different supply voltage and different frequencies, load capacitors, and temperatures. The simulation results confirm that the proposed design is the fastest 4-to-2 compressor in different working circumstance.

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Section: Related Workmentioning

confidence: 99%

A New High Speed Carbon Nanotube Field Effect Transistor-Based Structure for 4-to-2 Compressor Cell

Bagherizadeh

Eshghi

2016

j comput theor nanosci

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“…A 5-2 compressor gets five primary inputs a 1 , a 2 , a 3 , a 4 , a 5 and C in1 , C in2 as carry-input bits from a neighboring one lower significant cell with weights of one and generates Sum and Carry outputs with weights of one and two and generates C out1 and C out2 outputs as carry-out bits with weights of two. …”

Section: Proposed Structurementioning

confidence: 99%

“…In conclusion, the latency to generate C out2 includes 1 gate level delay plus 1 TG and 1 ready gate-channel transistor. According to Table I, for 5 . So, it is obtained as:…”

Section: Proposed Structurementioning

confidence: 99%

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CMOS implementation of a new high speed 5-2 compressor for parallel accumulations

Tohidi

Abolhasani

Hadidi

et al. 2013

IEICE Electron. Express

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This paper presents a new high speed 5-2 compressor. It is designed based on a new truth table which leads to a simple structure. Also, the driving problems are reduced. Due to the similar paths from inputs to the outputs, there will be no need for extra buffers in low latency paths to equalize the delays and the power dissipation is decreased. Furthermore, by use of full swing logics, the speed of cascaded operations is enhanced. The latency of proposed design is 440 ps.

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“…One of the outputs of such structure (denoted as C out ) is horizontally sent to the next sitting compressor block with a higher binary bit position value [2]. Figure 1 illustrates the explained structure in which X1 -X4 constitute the main input bits while the fifth input comes from the previous compressor with a lower binary bit value [3].…”

Section: Introductionmentioning

confidence: 99%

CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers

Rahnamaei

2020

Informacije MIDEM

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In this article, the design procedure for high-speed 5-2 and 6-2 compressors, along with their analysis, has been discussed. With the help of the combinational logic consisting of the 4-2 compressor and 3-2 counter blocks, a high-performance structure for 6-2 compressor has been achieved, which shows significant speed improvement over previous architectures. The optimization has been carried out by reducing the carry rippling issue between the adjacent compressor structures. Also, the help of some modifications, the proposed 6-2 compressor will turn into a 5-2 compressor where the latency of the critical path has considerably been reduced, illustrating the superiority of designed circuits. The corresponding latencies of the proposed 5-2 and 6-2 structures are equal to 3.5 and 4 XOR logic gates, respectively, demonstrating speed boosting of 15% and 20% compared to the best-reported architectures. In addition, the power consumption and the transistor count of proposed circuits are have remained at a moderate level. Therefore, by considering the Power-Delay Product (PDP), our work will be a good choice for high-speed parallel multiplier design. Post-layout simulation results based on TSMC 90nm standard CMOS process and 0.9V power supply have been presented to confirm the correct functionality of the implemented compressors. These results have also been used as a fair comparison infrastructure between the proposed works and redesignated architectures of the previously reported schemes.

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A Novel and Very Fast 4-2 Compressor for High Speed Arithmetic Operations

Cited by 13 publications

References 2 publications

A New High Speed Carbon Nanotube Field Effect Transistor-Based Structure for 4-to-2 Compressor Cell

A New High Speed Carbon Nanotube Field Effect Transistor-Based Structure for 4-to-2 Compressor Cell

CMOS implementation of a new high speed 5-2 compressor for parallel accumulations

CMOS High-Performance 5-2 and 6-2 Compressors for High-Speed Parallel Multipliers

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