A novel approach to the design and implementation of very high-speed digit-serial modified-Booth multipliers

Rao, V.M.; Nourouzian, B.

doi:10.1109/mwscas.1996.594029

Cited by 1 publication

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“…Those works collectively showed that in many use cases bit-or digit-serial arithmetic can yield attractive tradeoffs between area and performance. While some of those studies evaluated serial designs tailored to specific VLSI processes or libraries [4] [6], most previous studies that evaluated FPGA designs did so independent of target architecture using vendors' synthesis tools [10][11] [14]. In contrast, our study evaluates low-level optimizations based on Xilinx 7-series resources.…”

Section: Previous Workmentioning

confidence: 99%

Revisiting Serial Arithmetic: A Performance and Tradeoff Analysis for Parallel Applications on Modern FPGAs

Landy

Stitt

2015

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

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Serial arithmetic cores reduce area compared to bitparallel alternatives, but are generally assumed to be inappropriate for high-performance FPGA applications due to a significant reduction in throughput. In this paper, we perform a performance and tradeoff analysis of Xilinx 7-series specialized architectures for a novel serial adder tree and multiplier. We show that these serial arithmetic architectures significantly improve functional density due to an average 2u clock speedup compared to bit-parallel alternatives, which provides attractive tradeoffs for different usage scenarios. We also show that serial arithmetic can surprisingly provide better performance than bit-parallel alternatives when replication is solely limited by an area constraint and not application parallelism or input bandwidth. We evaluate this performance improvement on several highly parallel sliding-window applications, showing average speedups of 4.8u and 4.4u compared to bit-parallel implementations over a variety of area constraints.

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Section: Previous Workmentioning

confidence: 99%