A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm

Pandey, Jai Gopal; Karmakar, Arindam; Shekhar, Chandra; Gurunarayanan, S.

doi:10.1109/vlsid.2014.58

Cited by 13 publications

(9 citation statements)

References 17 publications

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“…In [ 18 , 20 ], similar architectures of the Otsu algorithm in the Virtex-5 xc5vfx70t ffg1136-1 FPGA were deployed, available on the Xilinx ML-507 development platform. Both proposals were developed in VHDL, using fixed-point representation, operating at a clock frequency of

MHz.…”

Section: Related Workmentioning

confidence: 99%

“…Both proposals were developed in VHDL, using fixed-point representation, operating at a clock frequency of

MHz. The proposal described in [ 18 ] occupied 168 slices and 33 IOBs, while in [ 20 ], the implementation reached an area occupation of 161 slices, 21 IOBs, 72 Look-Up Tables (LUTs), 591 registers, 4 blocks of RAM (BRAMs), and 5 DSP48Es. In addition, Reference [ 20 ] presented results related to the processing time for a

image, with pixels represented by 8 bits.…”

Section: Related Workmentioning

confidence: 99%

“…The FPGA allows the exploitation of the algorithm parallelization and the development of dedicated hardware to obtain performance improvement [9][10][11][12][13][14][15]. However, FPGA implementations found in the literature are often developed with sequential processing schemes in some stages of the Otsu algorithm, limiting the hardware's processing speed [16][17][18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

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Fully Parallel Implementation of Otsu Automatic Image Thresholding Algorithm on FPGA

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2021

Sensors

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This work proposes a high-throughput implementation of the Otsu automatic image thresholding algorithm on Field Programmable Gate Array (FPGA), aiming to process high-resolution images in real-time. The Otsu method is a widely used global thresholding algorithm to define an optimal threshold between two classes. However, this technique has a high computational cost, making it difficult to use in real-time applications. Thus, this paper proposes a hardware design exploiting parallelization to optimize the system’s processing time. The implementation details and an analysis of the synthesis results concerning the hardware area occupation, throughput, and dynamic power consumption, are presented. Results have shown that the proposed hardware achieved a high speedup compared to similar works in the literature.

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MHz.…”

Section: Related Workmentioning

confidence: 99%

“…Both proposals were developed in VHDL, using fixed-point representation, operating at a clock frequency of

image, with pixels represented by 8 bits.…”

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Fully Parallel Implementation of Otsu Automatic Image Thresholding Algorithm on FPGA

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2021

Sensors

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“…Visando também eliminar divisões e multiplicações do método de Otsu, os trabalhos apresentados em [16], [17], [18] e [19] propõem a implementação da técnica com uso de funções logarítmicas. Em [16] e [18] são apresentadas duas implementações, uma da técnica direta e outra utilizando função logarítmica, sendo analisado em ambos a utilização de recursos do hardware para cada implementação.…”

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“…Em [17] e [19] as arquiteturas desenvolvidas são bastante semelhantes, sendo ambas implementadas em VHDL utilizando representação em ponto-fixo. Os dois projetos utilizam FPGA Xilinx Virtex-5 xc5vfx70tffg1-136-1 disponível na plataforma de desenvolvimento ML-507 da Xilinx, operando com um clock de 25,175 MHz.…”

Section: Estado Da Arteunclassified

Proposta de Implementação em Hardware do Algoritmo de Otsu Aplicado ao Rastreamento em Tempo Real de Vermes

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2021

Anais Do XII Computer on the Beach - COTB '21

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This work proposes an implementation in Field Programmable GateArray (FPGA) of the Otsu’s method applied to real-time trackingof worms called Caenorhabditis elegans. Real-time tracking is necessaryto measure changes in the worm’s behavior in response totreatment with Ribonucleic Acid (RNA) interference. Otsu’s methodis a global thresholding algorithm used to define an optimal thresholdbetween two classes. However, this technique in real-time applicationsassociated with the processing of high-resolution videoshas a high computational cost because of the massive amount ofdata generated. Otsu’s algorithm needs to identify the worms ineach frame captured by a high-resolution camera in a real-timeanalysis of the worm’s behavior. Thus, this work proposes a highperformanceimplementation of Otsu’s algorithm in FPGA. Theresults show it was possible to achieve a speedup up to 5 timeshigher than similar works in the literature.

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Design and Implementation of a Novel Eye Gaze Recognition System Based on Scleral Area for MND Patients Using Video Processing

Rupanagudi¹,

Bhat²,

Karthik³

et al. 2015

Advances in Intelligent Systems and Computing

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A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm

Cited by 13 publications

References 17 publications

Fully Parallel Implementation of Otsu Automatic Image Thresholding Algorithm on FPGA

Fully Parallel Implementation of Otsu Automatic Image Thresholding Algorithm on FPGA

Proposta de Implementação em Hardware do Algoritmo de Otsu Aplicado ao Rastreamento em Tempo Real de Vermes

Design and Implementation of a Novel Eye Gaze Recognition System Based on Scleral Area for MND Patients Using Video Processing

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