A Novel Architecture for Implementation of Quasi Delay Insensitive Finite State Machines

Oliveira, Duarte L.; Verducci, Orlando; Torres, Vitor L. V.; Saotome, Osamu; Moreno, Robson Luiz; Brandolin, Joao B.

doi:10.1109/intercon.2018.8526442

Cited by 2 publications

(1 citation statement)

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“…The technology scaling imposes various limitations on synchronous circuits [49,[57][58][59], and the asynchronous design approach is being reconsidered by various researchers to overcome the limitations due to the presence of the clock signal. The demand for portable electronic devices with minimal power consumption [60] without compromising the processing speed and silicon area is another major concern [61,62]. Various asynchronous digital circuits are designed and commercialized by the leading companies such as IBM, Intel, Philips Semiconductors, Sun Microsystems (now Oracle), etc., [63][64][65][66][67] over the last two decades with considerable cost benefits.…”

Section: Introductionmentioning

confidence: 99%

Asynchronous Floating-Point Adders and Communication Protocols: A Survey

2020

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Addition is the key operation in digital systems, and floating-point adder (FPA) is frequently used for real number addition because floating-point representation provides a large dynamic range. Most of the existing FPA designs are synchronous and their activities are coordinated by clock signal(s). However, technology scaling has imposed several challenges like clock skew, clock distribution, etc., on synchronous design due to presence of clock signal(s). Asynchronous design is an alternate approach to eliminate these challenges imposed by the clock, as it replaces the global clock with handshaking signals and utilizes a communication protocol to indicate the completion of activities. Bundled data and dual-rail coding are the most common communication protocols used in asynchronous design. All existing asynchronous floating-point adder (AFPA) designs utilize dual-rail coding for completion detection, as it allows the circuit to acknowledge as soon as the computation is done; while bundled data and synchronous designs utilizing single-rail encoding will have to wait for the worst-case delay irrespective of the actual completion time. This paper reviews all the existing AFPA designs and examines the effects of the selected communication protocol on its performance. It also discusses the probable outcome of AFPA designed using protocols other than dual-rail coding.

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