A Novel Array-Based Test Methodology for Local Process Variation Monitoring

Luo, Tseng-Chin; Chao, Mango C.-T.; Wu, Michael S.-Y.; Li, Kuo-Tsai; Hsia, Chin; Tseng, Henry; Fisher, Philip A.; Huang, Chao-Jen; Chang, Yao‐Ting; Pan, S.C.; Young, K.K.

doi:10.1109/tsm.2010.2095891

Cited by 13 publications

(4 citation statements)

References 15 publications

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“…In a traditional parametric tester V t measurement, the SMUs are configured as voltage sources, which can be modeled as unity-gain buffers as shown in Fig. 1 [19]. V t can be defined as the gate-to-source potential required to drive the threshold drain-to-source current, I ds (V t ) = (I 0, n) * W eff /L eff for n-FET, and…”

Section: A Measuring Constant Current V T Using a Binary Search Algomentioning

confidence: 99%

“…With appropriate design of access circuitry, however, array test structures can perform accurate measurements of most key parametrics, such as I dsat , V tsat , and many other key points on the I -V characteristic, and over a thousand DUTs can easily fit in a single scribeline test structure. The design measures required to achieve optimal accuracy in array-based test structures, as well as the details of the array-based test structure employed in this paper, were discussed at greater length in [19]. As discussed below, the test time reduction by our proposed test algorithm can be readily combined with array-based test structures to perform characterization of a large number of DUTs, which would otherwise be extremely challenging in a manufacturing environment because of prohibitively long test time.…”

Section: Implementation For Array Test Structure V T Measurementmentioning

confidence: 99%

“…12 shows the proposed transistor array with 16 × 64 = 1024 test units. In-depth discussion of the design and operation of the array was discussed in [19], but its function is summarized in brief below. Each test unit consists of a few transmission gates and one DUT (a FET in this example).…”

Section: Implementation For Array Test Structure V T Measurementmentioning

confidence: 99%

“…The PCM testline has device-under-tests (DUTs) and I/O pads aligned along a straight line and uses four I/O pads to measure each DUT. Thus, both the height of a PCM testline and the required spacing in a scribe line are limited [19]. Only a relatively limited number of DUTs can be placed in such a testline configuration because of the limited number of I/O pads.…”

Section: Introductionmentioning

confidence: 99%

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Fast Transistor Threshold Voltage Measurement Method for High-Speed, High-Accuracy Advanced Process Characterization

Luo

Chao

Tseng

et al. 2014

IEEE Trans. VLSI Syst.

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As process technologies continually advance, process variation has greatly increased and has gradually become one of the most critical factors for IC manufacturing. Furthermore, these increasingly complex processes continue to make greater use of stressors for mobility enhancement, thus requiring large volumes of data for extensive characterization of layoutdependent effects (LDE) for validation of both SPICE models and design for manufacturing. Transistor threshold voltage (V t) is a commonly used parameter both for characterization during process development and for monitoring of volume manufacturing. To adequately quantify local process variation or LDE, V t must be measured for a sufficiently large number of deviceunder-tests (DUTs) to obtain a statistically representative sample population. The number of V t measurements required to obtain such a statistically significant result, however, requires extremely long testing time, especially for array-based test structure designs including thousands of DUTs. In this paper, we present a very fast threshold voltage measurement methodology using an operational amplifier-based source-measure unit test configuration, which greatly improves testing efficiency and accuracy, and is not sensitive to process variation. The proposed test methodology can improve V t testing time by a factor of 5-10 relative to the commonly used binary-search algorithm, and by a factor of ∼2 relative to an optimized interpolation algorithm, and achieves better accuracy (standard deviation of V t = 0.15 mV, versus typical accuracy of ∼ 0.5 mV for the two algorithms mentioned). Furthermore, the layout and configuration of conventional test structures need not be modified to adapt the proposed methodology. The measured results from the most advanced process technology nodes demonstrate the testing efficiency and accuracy of the proposed test structure in characterizing the large number of DUTs required for quantifying process variation or LDEs.

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Section: A Measuring Constant Current V T Using a Binary Search Algomentioning

confidence: 99%

Section: Implementation For Array Test Structure V T Measurementmentioning

confidence: 99%

Section: Implementation For Array Test Structure V T Measurementmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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