A novel array-based test methodology for local process variation monitoring

Luo, Tseng-Chin; Chao, Mango C.-T.; Wu, Michael S.-Y.; Li, Kuo-Tsai; Hsia, Chin; Tseng, Henry; Huang, Chao-Jen; Chang, Yao‐Ting; Pan, S.C.; Young, K.K.

doi:10.1109/test.2009.5355656

Cited by 4 publications

(1 citation statement)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…One popular approach to solve this background leakage issue is to force the gate voltage of the unselected DUTs to a slight negative bias through certain control scheme [3] [7] [11]. Another approach is to elevate a proper voltage bias of all four DUT terminals such that the leakage paths from the transmission gates can be balanced [9].…”

Section: Introductionmentioning

confidence: 99%

Predicting Vt mean and variance from parallel Id measurement with model-fitting technique

Tsai

Lee

Lin

et al. 2016

2016 IEEE 34th VLSI Test Symposium (VTS)

Self Cite

View full text Add to dashboard Cite

To measure the variation of device Vt requires long test for conventional WAT test structures. This paper presents a framework that can efficiently and effectively obtain the mean and variance of Vt for a large number of DUTs. The proposed framework applies the model-based random forest as its core model-fitting technique to learn a model that can predict the mean and variance of Vt based on only the combined I d measured from parallel connected DUTs. The experimental results based on the SPICE simulation of a UMC 28nm technology demonstrate that the proposed modelfitting framework can achieve a more than 99% R-squared for predicting both of Vt mean and variance. Compared to conventional WAT test structures using binary search, our proposed framework can achieve 42.9X speedup in turn of the required iterations of I d measurement per DUT.

show abstract

Section: Introductionmentioning

confidence: 99%