2015
DOI: 10.15866/iree.v10i2.5089
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A Novel BIST Circuit for Testing and Analysis Parametric Faults in PLL

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“…In the latter, we compare the results of the proposed modified BIST and those obtained in previous work [12]. The proposed on-chip BIST scheme shows fault coverage of 100% for catastrophic faults and process variations for the PLL.…”
Section: ) Discharge Test Modementioning
confidence: 87%
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“…In the latter, we compare the results of the proposed modified BIST and those obtained in previous work [12]. The proposed on-chip BIST scheme shows fault coverage of 100% for catastrophic faults and process variations for the PLL.…”
Section: ) Discharge Test Modementioning
confidence: 87%
“…In our preceding work [12], three multiplexors and two delay cells are used. In order to further reduce the area occupied by the test circuit, we propose a new test stimulus generator circuit as shown in Fig.…”
Section: B Test Stimulus Generator Circuitmentioning
confidence: 99%
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