Charge Pump controlled with three states of a Phase Frequency Detector is an essential building block of Phase Locked Loops (PLLs). ChargePump-Phase Locked Loops are usually used in diverse applications, such as on chip clock synthesis, symbol timing recovery for serial data streams and generation of frequency agile high frequency carrier signals. This paper describes an effective structure of a Charge Pump (CP) and a Phase Frequency Detector (PFD) circuits which are the key blocks for the design of PLLs. The behavioral modeling has been synthesized from a hardware description language (VHDL-AMS). This CP-PFD circuit was designed with 0.35μm AMS CMOS technology. Electrical simulation results are shown using ADS platform.

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Analog and mixed architectures design with high performance suffered from many difficulties due to low power supply, consumption, and the trend toward reducing the size of the circuit. Currently, these performances are considered one of the main constraints in analog design. Characterized and designed of mixed circuits such as Charge Pump-Phase Locked Loops (CP-PLLs) is a challenge in mixed-signal integrated circuits design. In this paper, an effective CMOS CP-PLLs architecture for RF applications that operates at a low power supply 2V into a large range frequency is presented. The proposed CP-PLLs architecture has two novel design blocks which are respectively Phase Frequency Detector (PFD) and Voltage Controlled Oscillator (VCO). The key advantage of the two novel designs is that uses a simple circuit, provide more stable operation compared with other structures recently used and reduce the chip area overhead. Also, the novel VCO design solved the problems caused by recent structures. The CP-PLLs is designed and evaluated using electrical simulator tolls (ADS) with 0.35μm AMS CMOS technology. Simulations results show a good performance and the effectiveness of the proposed structure.