A Novel BJT Structure Implemented Using CMOS Processes for High-Performance Analog Circuit Applications

Jung, Yi-Jung; Park, Byoung-Seok; Kwon, Hyuk-Min; Kwon, Sung-Kyu; Jang, Jae-Hyung; Kwak, Ho‐Young; Chung, Yi-Sun; Lee, Jung Hwan; Lee, Hi‐Deok

doi:10.1109/tsm.2012.2192749

Cited by 8 publications

(4 citation statements)

References 16 publications

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“…The NOI transconductance is poor but constant along a large gate voltage range. The Tunnelpin-FET presents different transconductance: 180 μA/V at V G = 2 V and 2 μA/V at V G = 0.75 V and strongly decreases at V G = 0.5 V. A lower but constant transconductance of the NOI devices is sometimes more valuable than a transconductance with high oscillations, for some analog applications, like linear circuits, [36].…”

Section: Table IImentioning

confidence: 99%

Semiconductor Materials Optimization for a TFET Device With Central Nothing Region on Insulator

Ravariu

2013

IEEE Trans. Semicond. Manufact.

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This paper presents the work regimes of an atypical SOI device. The proposed device belongs to the Tunneling FET class, but the main body is a vacuum cavity. Each layer has a maximum of 10 nm. Firstly, the paper studies the static characteristics of the proposed device by simulations for different semiconductor materials: Si, SiC and Ge, with different doping concentrations, in different bias conditions. Secondly, some key parameters are defined in order to establish the boundary of the different work regimes. The normal work regime is conditioned by the useful tunneling occurrence, maximum transconductance, and current capability, far away from the insulator breakdown that means a non-useful back-gate leakage current. The simulations reveal optimum Semiconductor-Vacuum-Semiconductor structures On Insulator for heavy doped films, thin oxides, and larger band gap materials. An optimum balance is offered by the SiC device with 10 nm thickness on 10 nm insulator with a cavity width of 2 nm.

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Section: Table IImentioning

confidence: 99%

Semiconductor Materials Optimization for a TFET Device With Central Nothing Region on Insulator

Ravariu

2013

IEEE Trans. Semicond. Manufact.

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“…The standard deviation of the AHA structure and the conventional MIM capacitor is proportional to 1/sqrt (W × L, capacitor area) as shown in Fig. 5 [12]. The extracted matching coefficients, which is defined as the slope of σ ( C/C)(%) versus 1/sqrt (W × L) as shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

A Study of Dielectric Relaxation and Capacitance Matching of ${\rm Al}_{2}{\rm O}_{3}/{\rm HfO}_{2}/{\rm Al}_{2}{\rm O}_{3}$ MIM Capacitors

Han

Kwon

et al. 2013

IEEE Electron Device Lett.

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Key analog characteristics such as dielectric relaxation and capacitance matching for Al 2 O 3 /HfO 2 /Al 2 O 3 (AHA) metal-insulator-metal (MIM) capacitors were analyzed for highperformance analog circuit applications. Although the dc characteristics of AHA MIM capacitor were acceptable for analog operation, the variation of the quadratic voltage coefficient (α) under constant voltage stress (CVS) and the dielectric relaxation remained problematic. The dependence of α for AHA MIM capacitor decreased gradually under CVS and the dielectric relaxation of AHA MIM capacitor was greater than that of conventional MIM capacitor, which was due to the effect of preexisted traps in high-k dielectric. The extracted matching coefficient of AHA MIM capacitor was, however, 0.698% μm, which was low enough to be used for analog/mixed signal/radio frequency application.Index Terms-Analog/mixed signal, dielectric relaxation, electrical performance, floating gate, matching, metal-insulatormetal (MIM) capacitor.

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“…This structure was compared with the conventional structure in terms of matching performance, and it was found that the improvement of matching performance of this structure was mainly due to the reduction of the deep well effect. To improve matching characteristics, reducing the base region and minimizing the impact of DNW by decreasing the distance between the collector and emitter contact regions have been demonstrated as effective strategies in Figures 1-2, as reported in [7]. Nowadays, the CMOS layout structure is more and more diverse, and the technology is more and more mature.…”

Section: Introductionmentioning

confidence: 99%

Design and optimization of CMOS layout structure for improved semiconductor device performance

Huang

2023

J. Phys.: Conf. Ser.

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CMOS layout structure plays a very important role in the field of semiconductor. Since the invention of CMOS technology in the 1970s, engineers have developed many other CMOS layout technologies based on it. This paper will also focus on the CMOS transistor layout structure, focusing on the analysis of three more important structures, demonstrating their impact on the performance of semiconductor devices. Before that, this paper will first introduce the basic theory of CMOS, such as the drift and diffusion of charge carriers in PN junctions, and the working principle of PMOS and NMOS, so as to facilitate us to further describe the optimization and improvement of CMOS structure. Then, the performance and characteristics of each structure are introduced in detail, and finally the comparison is made to highlight their advantages in technology and performance compared with traditional structures. In the future, CMOS structure layout will also become a hot spot, constantly creating more reasonable and advanced structures to improve semiconductor performance.

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A Novel BJT Structure Implemented Using CMOS Processes for High-Performance Analog Circuit Applications

Cited by 8 publications

References 16 publications

Semiconductor Materials Optimization for a TFET Device With Central Nothing Region on Insulator

Semiconductor Materials Optimization for a TFET Device With Central Nothing Region on Insulator

A Study of Dielectric Relaxation and Capacitance Matching of ${\rm Al}_{2}{\rm O}_{3}/{\rm HfO}_{2}/{\rm Al}_{2}{\rm O}_{3}$ MIM Capacitors

Design and optimization of CMOS layout structure for improved semiconductor device performance

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