Semiconductor Materials Optimization for a TFET Device With Central Nothing Region on Insulator

Ravariu, Cristian

doi:10.1109/tsm.2013.2258411

Cited by 20 publications

(13 citation statements)

References 30 publications

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“…Tunnel-FETs with horizontal p-i-n islands offer swing less than 60 mV/decade, surpassing the MOSFET limit [4], and vacuum microdevices still get minimum noise [5]. Recently, an alternative nanostructure composed by semiconductor-vacuum-semiconductor on insulator, also known as nothing on insulator (NOI) device, was proposed [6]- [8]. Due to the tunneling conduction through a vacuum cavity, besides to a configuration on insulator, the NOI device makes the link among vacuum, Silicon On Insulator (SOI), and tunnel devices.…”

Section: Introductionmentioning

confidence: 99%

Deeper Insights of the Conduction Mechanisms in a Vacuum SOI Nanotransistor

Ravariu

2016

IEEE Trans. Electron Devices

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This paper presents new work regimes accompanied by specific conduction models of an SOI nanotransistor with a vacuum cavity. The tunneling mechanisms are separately explored to find out the dominant mechanism. Afterward, the simulations show for the first time two firms on and off states under the gate command. Strong and weak tunneling regimes are emphasized. For the first time, a quasi-saturation region of the I D -V DS curves is obtained for V DS > 6 V. Different device structures are compared. The best configuration has the swing of 290 mV/decade, threshold voltage of −0.5 V and maximum I ON /I OFF ratio of 10 10 , which is a real gain among the vacuum transistors. Some applications as vacuum diode, switch under the gate command or action as parasitic device are emphasized. ).This paper has supplementary downloadable multimedia material available at http://ieeexplore.ieee.org provided by the authors. This includes a PNG file that shows the lattice temperature map across the NOI(a) transistor, proving no temperature gradient occurs and consequently the energy balance (activated by KSN=KSP=-1 as default value), or simplified hydrodynamic models (activated by KSN=KSP=0) offers similar currents. The total size of the files is 24.2 KB Color versions of one or more of the figures in this paper are available online at

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Section: Introductionmentioning

confidence: 99%

Deeper Insights of the Conduction Mechanisms in a Vacuum SOI Nanotransistor

Ravariu

2016

IEEE Trans. Electron Devices

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“…Therefore, the back and front gates from SOI architecture [12] are re-named here as bottom and top gates, accordingly to the TFT terminology, [6,7].…”

Section: The Organic-tft Conceptmentioning

confidence: 99%

Different Work Regimes of an Organic Thin Film Transistor OTFT and Possible Applications in Bioelectronics

Ravariu

Dragomirescu²

2015

BIO

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This paper presents an organic semiconductor transistor, with a vertical current modulation and a horizontal conduction. The simulations show a stronger top gate influence and establish four work regimes, depending on the top and bottom gates biasing. In the most favorable regime for the holes channel, under the reverse biased n + p junction, the holes/electrons current densities ratio reaches 0.168/269. However, an ambipolar OTFT function occurs under the reverse biasing of the vertical junction, with a top n-layer and a bottom p-layer. Due to the asymmetrical doping profile, the n + channel conduction prevails in all the regimes. Therefore, the maximum current density of 1900A/cm 2 is ensured by a double n channel, when both gates are positive biased. After simulations, three distinct work regimes are revealed by this single device: a SOI behavior with volume channel, a JFET with neutral median channel and an OTFT with one or more interface channels.

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“…Quantum-well MOSFETs [8] 81 InGaZnO-Based Thin-Film Transistor [9] 85 Al 0.83 In 0.17 N/AlN/GaN MOS-HEMT on SiC Substrate [10] 40 The nothing-on-insulator (NOI) transistor [11,12] 50 Metal-Ferroelectric-Insulator [13] 150 Double-Gate Strained-Ge Heterostructure Tunneling FET [14] 52 Fe-FET with P(VDF-TrFE)/SiO2 Gate Stack [13] 13 Metal-Ferroelectric-Metal-Oxide-Semiconductor FET [15] 46-58 Vertical Si-Nanowire n-Type Tunneling FETs [16] 30 would bring transformative change in the performance and energy efficiency of both ultra-low-power and high performance micro-/nano-electronic applications. We formally named this new device Silicon-on-Ferroelectric Insulator Field Effect (SOFFET) [20,21].…”

Section: Structurementioning

confidence: 99%

“…Using the structure of Fig. 2 we can derive a first order approximation of V TH as illustrated in (8)- (11). From the derived model (11), it is observed that the threshold voltage of the proposed PD-SOFFET depends on the thickness of the ferroelectric material.…”

Section: Threshold Voltage Of the Proposed Pd-soffetmentioning

confidence: 99%