A Novel Bootstrapped Switch Design, Applied in a 400 MHz Clocked &amp;#x00394;&amp;#x003A3; ADC

Cornelissens, Koen; Steyaert, Michiel

doi:10.1109/icecs.2006.379645

Cited by 4 publications

(2 citation statements)

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“…For the same reason, the bulk is connected first to the input before bootstrapping the gate at the start of the track phase. Although the switching of the bulk can be considered in the same way as clock feedthrough [8] using formula 1, simulations indicate that its impact can be neglected at 6-b accuracy. In the formula, V in is the differential input signal and ∆V is the change in differential output.…”

Section: B Simulated Performance Using Bulk Switchingmentioning

confidence: 99%

A 6-b UWB subsampling track & hold with 5.5-GHz ERBW in 40 nm CMOS

Strackx

D’Agostino

Leroux

et al. 2014

2014 IEEE Radio Frequency Integrated Circuits Symposium

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This paper presents an ultra wideband track and hold (T/H) circuit using direct RF subsampling for radar applications. The circuit enables digitization of the whole received UWB pulse instead of a sole distance measurement used in correlating receivers. In this way, more target information is acquired for further digital processing. Subsampling was applied to achieve a low power concumption of 1.4 mW which includes the T/H core and clock generator. The circuit operates on a rail-to-rail input using the bootstrapping technique. To avoid reliability issues caused by bootstrapping the sampling switch, bulk switching and precharge techniques are introduced. An effective resolution bandwidth of 5.5-GHz was measured with an accuracy of 6b. The track and hold circuit has been implemented in 40 nm CMOS.

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Section: B Simulated Performance Using Bulk Switchingmentioning

confidence: 99%

A 6-b UWB subsampling track & hold with 5.5-GHz ERBW in 40 nm CMOS

Strackx

D’Agostino

Leroux

et al. 2014

2014 IEEE Radio Frequency Integrated Circuits Symposium

View full text Add to dashboard Cite

show abstract

“…This allows easier reconfigurability of this filter [15]. In deep-submicron CMOS, the intrinsic speed of the technology can be used to maintain a high OSR, even for large signal bandwidths [16]. Figure 6.7 shows different methods to make a ADC reconfigurable.…”

Section: 521mentioning

confidence: 99%