A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs

An Optimization Mechanism Intended for Static Power Reduction Using Dual‐VthTechnique

“…All cells belonging to the substitute candidates list must have a maximum fan-out equal to or lower than the circCell maximum fan-out and higher than half of this value. These parameters were defined after exhaustive simulations in order to obtain the best optimization results, based on [16]. The pseudocode for the creation of the substitute candidates list is described in Algorithm 2.…”

“…However, the application of an ILP-based approach may not be suitable for large designs, because it is a very time-consuming optimization approach. A technique for reduction of leakage power of 90 nm and 65 nm integrated circuits with multimillions gates by exchanging low V th voltage (LVT) cells belonging to less critical paths of the circuit by HVT cells has been proposed by Gupta et al [16]. This work targets the problem of long runtime and static power consumption using a heuristic method.…”

“…Additionally, this algorithm aims at optimizing the netlist of an initial multi-V th circuit. Unlike path-based approaches (in general, by optimizing the noncritical paths of the gate circuits), in [16] it does not update the timing at each cell replacement. Even with this feature, for circuits with multimillions gates, the algorithm runtime becomes a dominant factor during design flow.…”