2018
DOI: 10.1016/j.sse.2018.07.005
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A novel charge recycle read write assist technique for energy efficient and fast 20 nm 8T-SRAM array

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Cited by 16 publications
(4 citation statements)
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“…To investigate the effect of oxide (SiO2) layer thickness, the Silicon dioxide (SiO2) material thickness was altered in the range of 0.8 nm to 3 nm, while preserving the overall dimension of the FinFET static at 30 nm. To perceive the influence of the oxide layer thickness on numerous vital performance parameters like drain current, transconductance, transconductance generation factor, parasitic capacitances, cut-off frequency, maximum frequency, gain bandwidth, energy and power consumption [22][23][24], etc., SOI FinFETs were simulated and investigated for structures with different oxide layer thickness.…”
Section: Device Structure and Simulation Setupmentioning
confidence: 99%
“…To investigate the effect of oxide (SiO2) layer thickness, the Silicon dioxide (SiO2) material thickness was altered in the range of 0.8 nm to 3 nm, while preserving the overall dimension of the FinFET static at 30 nm. To perceive the influence of the oxide layer thickness on numerous vital performance parameters like drain current, transconductance, transconductance generation factor, parasitic capacitances, cut-off frequency, maximum frequency, gain bandwidth, energy and power consumption [22][23][24], etc., SOI FinFETs were simulated and investigated for structures with different oxide layer thickness.…”
Section: Device Structure and Simulation Setupmentioning
confidence: 99%
“…This technique isolates the read bit-lines from internal nodes, thereby consuming less energy, but at the cost of area overhead. An 8T SRAM cell with charge recycling read and write assist (CRRWA) technique [25] has also been presented, which reduces read and write energies when compared with 6T CMOS SRAM cells. This technique also introduces area overhead.…”
Section: Related Workmentioning
confidence: 99%
“…17 SRAMs are able to bypass the von-Neumann bottleneck while retaining energy efficiency. 18 The majority of a chip's area is taken up by SRAMs, according to ITRS. 19 Therefore, it is vital to develop SRAM arrays that are fast, stable, high density, and power efficient.…”
mentioning
confidence: 99%
“…19 Therefore, it is vital to develop SRAM arrays that are fast, stable, high density, and power efficient. 18 Since they are implanted inside the body, portable applications like pacemakers, hearing aids, and other medical implantable devices require less power-hungry SRAMs. 20 In addition to these, SRAM and other logic circuitry are used frequently in the design of IoT devices.…”
mentioning
confidence: 99%