A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design

Low-power multiple-bit upset tolerant memory optimization

“…Simply using the maximum ID as in [2] increases the power consumption because the word-line for the accessed row must enable all unselected cell's access transistors. This results in many "half " selected cells which increase the leakage power consumption and potentially disturb the read operation [10]. On the other hand, word-line segmenting allows us to not half select these cells and significantly reduce the memory power consumption.…”

“…If the read ], we must enable the entire row during operation in the ID=4 case. This will half select the all other bits in the row and increase power consumption [10]. Total memory power consumption with parity bits and ECC can be modeled by P mem = P array + P parity + P ECC .…”

Low-power half-select free single-ended 10 transistor SRAM cell

“…Chang et al proposed a D2AP 8T cell (Chang et al 2012a) which possesses improved writeability but faces read disturb. Joshi et al (2011) proposed a column-decoupled (CDC) 8T cell in which a column select signal was used with an extra inverter to mitigate the half-select issue. But the cell suffers from read-disturb.…”

An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability

“…Conventional 6T SRAMs suffer from stability degradation and are unable function properly below 0.7V [2]. Many subthreshold SRAMs have been reported [3][4][5][6][7][8][9]. The subthreshold 8T and 10T reported in [3,4,7,8] may not function correctly in subthreshold region when bit-interleaved structure is adopted because half-selected bitcells have the same degraded stability as conventional 6T.…”

“…The reported designs in [5,10] were able to achieve subthreshold operation with bit-interleaved structure but they required additional power overhead as the half-selected columns were always in pseudo read operation whenever the memory was accessed. The SRAMs in [6,9] were reported to be able to work in subthreshold with bitinterleaved structure and yet prevented half-selected column from being accessed. However, the reported design in [9] had to use dual-power supplies for the cell array which incurred additional power overhead and increased design complexity.…”