Low-power half-select free single-ended 10 transistor SRAM cell

Abstract

the proposed design consumes 1.38× lesser read power as compared to UDVS10T and 1.67× and 5.02× lesser write power as compared to DF9T and UDVS10T respectively. The proposed design shows 1.8 % improvement in read current variability when compared to DF9T. Lastly, the proposed cell shows 2.21× and 5.25× higher I READ /I LEAK as compared to DF9T and UDVS10T.

One‐sided 10T static‐random access memory cell for energy‐efficient and noise‐immune internet of things applications

“…15 Finally, Figure 7 (f) shows that the proposed bit-cell has improved by 10.24% (1.11 times) in the mean value of the Read-SNM compared to the counterpart bit-cell in Sinha and Islam. 6 The read failure cases are also observed for the si-MOSFET technology-based bit-cell in Shakouri et al 8 In addition, it is observed that the minimum value of Read-SNM by the suggested bit-cell is about 128 mV, which is higher than the minimum requirement of Read-SNM (i.e., 25% of V dd ). Therefore, the result indicates that the proposed cell has a reasonably good read stability.…”

“…The results presented in Figure 7A show that the proposed bit‐cell with a higher Write‐SNM value has easier data writing than the cells considered for comparison in this study. After the proposed SRAM structure, the bit‐cell in Sinha and Islam 6 . Using the virtual ground design in similar design technology has a robust data transfer feature without the problem of writing conflict.…”

“…After the proposed SRAM structure, the bit-cell in Sinha and Islam. 6 Using the virtual ground design in similar design technology has a robust data transfer feature without the problem of writing conflict. After the proposed SRAM structure, the bit-cell in Sinha and Islam 6 with the same design technology and virtual ground scheme has a robust data bit transfer into the cell without the write conflict problem.…”

“…To prove the superiority of the proposed 10T SRAM's performance, various comparisons have been done based on the basic design metrics between the proposed cell and some SRAMs with the same number of transistors 6–8 . The Monte Carlo (MC) simulation results show that the proposed SRAM structure has improved by about 1.252, 1.196, and 1.152 times in terms of write/hold/read static noise margins (SNMs) compared to the best performing bit‐cells, respectively.…”

“…To prove the superiority of the proposed 10T SRAM's performance, various comparisons have been done based on the basic design metrics between the proposed cell and some SRAMs with the same number of transistors. [6][7][8] The Monte Carlo (MC) simulation results show that the proposed SRAM structure has improved by about 1.252, 1.196, and 1.152 times in terms of write/hold/read static noise margins (SNMs) compared to the best performing bit-cells, respectively. Also, the proposed memory cell shows the best results in other figure of merits (FoMs), such as process parameters, power supply voltage fluctuations, yield, and variability (μ/σ) against its counterpart SRAM bit-cells.…”