A novel compact model for on-chip stacked transformers in RF-CMOS technology

Abstract

A novel compact model for on-chip stacked transformers is presented. The proposed model topology gives a clear distinction to the eddy current, resistive and capacitive losses of the primary and secondary coils in the substrate. A method to analytically determine the non-ideal parasitics between the primary coil and substrate is provided. The model is further verified by the excellent match between the measured and simulated S-parameters on the extracted parameters for a 1 : 1 stacked transformer manufactured in a commercial RF-CMOS technology.

A novel method of analytically extracting model parameters for stacked transformers

“…Although there are many compact models proposed in the past years [6][7][8][9][10][11][12][13][14], techniques for analytical extraction of model parameters remain scarce. Because of the strong coupling among coils in a monolithic transformer, the analytical expression for terminal Z-parameters or Y-parameters is so complex that it is often impossible to extract elements in the model directly from measurement data, as is the case for more mature models of on-chip inductors [15][16][17].…”