A novel computational complexity and power reduction technique for H.264 intra prediction

Parlak, Mustafa; Adibelli, Yusuf; Hamzaoğlu, İlker

doi:10.1109/tce.2008.4711266

Cited by 32 publications

(24 citation statements)

References 8 publications

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“…The area of BLESS and buffered routers is compared by their resource usage in the FPGA. The power consumption of both routers is estimated by XPower [34], a commercial tool provided by Xilinx. XPower reports the power of individual design parts, including signals, clocks, logic, input/outputs, and static leakage power.…”

Section: Fpga Evaluation Hardware Platformmentioning

confidence: 99%

Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks

Cai¹,

Mai²,

Mutlu³

2015

Sixteenth International Symposium on Quality Electronic Design

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Abstract-Most existing packet-based on-chip networks assume routers have buffers to buffer packets at times of contention. Recently, deflection-based bufferless routing algorithms have been proposed as an alternative design to reduce the area, power, and complexity disadvantages associated with buffering in routers. While bufferless routing shows significant promise at an algorithmic level, these algorithms have not been shown to be efficiently implementable in practice. Neither were they extensively compared to existing buffered routing algorithms in realistic designs. This paper presents our comparative evaluation of and experiences with realistic FPGA and ASIC designs of state-of-the-art (1) virtual-channel buffered, (2) deflection-based bufferless, and (3) deflection-based buffered routing algorithms using two different network topologies and network sizes. We show that bufferless routing algorithms are implementable without significant complexity, and compare their performance, area, frequency, and power consumption to their buffered counterparts. Our results indicate that bufferless routing can lead to significant area (38%), power consumption (30%), and router cycle time (8%) reductions over the best buffered router implementation on 65nm ASIC design, while operating at higher frequency.

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Section: Fpga Evaluation Hardware Platformmentioning

confidence: 99%

Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks

Cai¹,

Mai²,

Mutlu³

2015

Sixteenth International Symposium on Quality Electronic Design

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“…The pixel equality based computation and power reduction technique we proposed in [4] exploits equality of neighboring pixels for simplifying the prediction calculations done by H.264 intra prediction modes. The pixel similarity based computation and power reduction technique we propose in this paper exploits similarity of neighboring pixels for simplifying the prediction calculations done by H.264 intra prediction modes.…”

Section: Proposed Pixel Similarity Based Techniquementioning

confidence: 99%

“…We proposed a pixel equality based technique for reducing the amount of computations performed by H.264 intra prediction algorithm and the power consumption of H.264 intra prediction hardware in [4]. In this paper, we propose a pixel similarity based technique for reducing the amount of computations performed by H.264 intra prediction algorithm and the power consumption of H.264 intra prediction hardware even further.…”

Section: Introductionmentioning

confidence: 99%

“…The technique proposed in [4] checks the equality of the neighboring pixels, and if the neighboring pixels used for calculating the predicted pixels by an intra 4x4 prediction mode are equal, the predicted pixels by this mode are equal to one of these neighboring pixels. Therefore, the prediction equations simplify to a constant value and prediction calculations for this mode become unnecessary.…”

Section: Introductionmentioning

confidence: 99%

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Pixel Similarity Based Computation and Power Reduction Technique for H.264 Intra Prediction

Adibelli

Parlak

Hamzaoğlu

2010

2010 International Conference on Field Programmable Logic and Applications

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H.264 intra prediction algorithm has a high computational complexity. This paper proposes a pixel similarity based technique for reducing the amount of computations performed by H.264 intra prediction algorithm and therefore reducing the power consumption of H.264 intra prediction hardware. The proposed technique performs a small number of comparisons among neighboring pixels of the current block before the intra prediction process. If the neighboring pixels of the current block are similar, the prediction equations of H.264 intra prediction modes are simplified for this block. The proposed technique reduces the amount of computations performed by 4x4 luminance prediction modes up to 68% with a small comparison overhead. This technique increases the PSNR slightly for some videos and it decreases the PSNR slightly for some videos. We also implemented an efficient 4x4 intra prediction hardware including the proposed technique using Verilog HDL. The proposed technique reduced the power consumption of this hardware up to 57%.

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“…It has shown greater coding efficiency than the existing video coding standards because it uses various coding tools including multiple reference frames, variable block sizes, rate-distortion optimization (RDO), and so on [2,3] . There are two types of prediction, intra and inter prediction, which reduce the spatial and temporal redundancy, respectively [4] .…”

Section: ⅰ Introductionmentioning

confidence: 99%

Intra Prediction Algorithm Using Adaptive Modes

Lim¹,

Lee²,

Kim³

et al. 2013

The Journal of Korea Information and Communications Society

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Key Words : adaptive mode selection, combined intra modes, simplified gradient modes, H.264/AVC, intra prediction ABSTRACT H.264/AVC has shown high coding efficiency by using various coding tools, including intra and inter prediction. However, there are still many more redundancy components in intra prediction than in inter prediction.In this paper, a novel intra prediction method is proposed with adaptive mode selection. The combined intra prediction modes and simplified gradient modes are added in order to refine the directional feature and gradation region. Suitable modes are selected according to the neighboring blocks that provide a high compression rate and lower computational complexity. The improvement of the proposed method is 1.96% in terms of the bitrate, 0.25 dB in PSNR, and 1.72 times in terms of the computational complexity.

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A novel computational complexity and power reduction technique for H.264 intra prediction

Cited by 32 publications

References 8 publications

Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks

Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks

Pixel Similarity Based Computation and Power Reduction Technique for H.264 Intra Prediction

Intra Prediction Algorithm Using Adaptive Modes

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