Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks

Cai, Yu; Mai, Ken; Mutlu, Onur

doi:10.1109/isqed.2015.7085472

Cited by 16 publications

(9 citation statements)

References 41 publications

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“…Hence there is a need for bufferless routers, which eliminate input and output buffers [11]. Various bufferless routing algorithms have been proposed to overcome the disadvantages of a buffered router [9,[16][17][18][19][20][21]. Cheap interconnect partially permuting router (CHIPPER) and bufferless router (BLESS) are the best examples of bufferless routers [18][19][20].…”

Section: Implementation Of Single-node Noc Routermentioning

confidence: 99%

“…Various bufferless routing algorithms have been proposed to overcome the disadvantages of a buffered router [9,[16][17][18][19][20][21]. Cheap interconnect partially permuting router (CHIPPER) and bufferless router (BLESS) are the best examples of bufferless routers [18][19][20]. Cai et al [20] prove that bufferless routing saves up to 30% power consumption and 38% area reduction in mesh or torus topology as compared with buffered architecture.…”

Section: Implementation Of Single-node Noc Routermentioning

confidence: 99%

“…Cheap interconnect partially permuting router (CHIPPER) and bufferless router (BLESS) are the best examples of bufferless routers [18][19][20]. Cai et al [20] prove that bufferless routing saves up to 30% power consumption and 38% area reduction in mesh or torus topology as compared with buffered architecture. CHIPPER NoC implementation shows that it reduces average network power by 54% and area by 36.2% for 8 × 8 mesh topology when compared with buffered routing [18].…”

Section: Implementation Of Single-node Noc Routermentioning

confidence: 99%

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Modified X–Y routing for mesh topology based NoC router on field programmable gate array

Shahane

Pisharoty

2019

IET Circuits, Devices & Systems

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Network on chip (NoC) has been proposed as an enormously scalable solution to address communication problems in system on chip (SoC). The interconnections among multiple cores/multiple Intellectual Property modules on a chip have a major impact on communication and performance of the chip design in terms of area, throughput, latency and power. Hence, an efficient design of the NoC interconnect is of paramount importance. In this study, a novel idea of the NoC router using a singleside buffer in the input block and a programmable priority encoder in the scheduler is discussed and a 4 × 4 mesh topology based router design is implemented on a field programmable gate array device using these blocks. This gives an area optimisation of the router due to the use of a small buffer. Furthermore, a modified X-Y routing algorithm is discussed and implemented for the 8 × 8 mesh topology-based router. The result shows that the modified X-Y routing algorithm requires only two hops to reach any source destination pair resulting in latency optimisation of the NoC router. Thus, the router design with a single buffer and a modified X-Y routing algorithm provides the best solution for area and latency optimisation.

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Section: Implementation Of Single-node Noc Routermentioning

confidence: 99%

Section: Implementation Of Single-node Noc Routermentioning

confidence: 99%

Section: Implementation Of Single-node Noc Routermentioning

confidence: 99%

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Modified X–Y routing for mesh topology based NoC router on field programmable gate array

Shahane

Pisharoty

2019

IET Circuits, Devices & Systems

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“…FPGA design consumes larger static power than the ASIC design due to excessive leakage currents [21][22][23], which is due to more number of transistors per logic. Other components, which are responsible for larger power consumption, are circuits used to provide flexibility to FPGA, number of configuration bits, lookup-tables (LUTs), and presence of large number of programmable switches.…”

Section: Power Consumption In Sram-based Fpgasmentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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The design of low-power SRAM cell becomes a necessity in today's FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAMbased FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA.

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“…Therefore, there is a bufferless router requirement that prevents buffering in input and output ports [8]. It has been proposed that various bufferless routing algorithms resolve the drawbacks of a buffered router [9]- [15].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of Single Node NoC Router using Small Side Buffer in Input Block and iSLIP Scheduler

Shahane¹

2020

IJATCSE

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Network on chip (NoC) has been recommended as an emerging alternative for scalability and performance needs of next generation System on chips (SoCs). NoCs are actually forecast to solve the bus based interconnection problem of SoC where large numbers of Intellectual property modules (IPs) are incorporated on a single chip for much better results. NoC provides a solution for communication infrastructure for SoC. The router is a foremost element of NoC which significantly impacts the performance of NoC. The architecture of router consists of an input port with buffers, arbiter, crossbar as well as an output port.The input block of NoC router requires buffers to keep the new data packets. These buffers improve the overall performance of the router in terms of throughput however they consume far more area and power. Bufferless deflection routing will be the solution for improvement in power efficiency, but latency might increase due to unnecessary hopping of data packets. Therefore use of small buffer will help to optimize latency and area in the router design. One more issue of router design is scheduler which allows contention free transfer of data packets among several IP modules or perhaps processors. For starvation free scheduling, Iterative Serial in Line Protocol (iSLIP) scheduler with programmable priority encoder provides best solution. The proposed design of high performance single node router with small side buffer in the input block and iSLIP scheduler has been implemented on FPGA in this paper.

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Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks

Cited by 16 publications

References 41 publications

Modified X–Y routing for mesh topology based NoC router on field programmable gate array

Modified X–Y routing for mesh topology based NoC router on field programmable gate array

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Design and Implementation of Single Node NoC Router using Small Side Buffer in Input Block and iSLIP Scheduler

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