Field - Programmable Gate Array 2017
DOI: 10.5772/67257
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Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Abstract: The design of low-power SRAM cell becomes a necessity in today's FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAMbased FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect… Show more

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