A Novel Cross-Latch Shift Register Scheme for Low Power Applications

Kuo, Po-Yu; Sheu, Ming‐Hwa; Tsai, Chang-Ming; Tsai, Ming-Yan; Lin, Jin-Fa

doi:10.3390/app11010129

Cited by 5 publications

(4 citation statements)

References 33 publications

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“…The proposed model attains PDP value of 124. The power consumption in reference (14) is 794 µW, in reference (15) is 504 µW, in reference (16) is 149 µW and the proposed model consume 0.502 µW.…”

Section: Existing Models Comparison Resultsmentioning

confidence: 99%

“…The shift register eliminates the need for a single pulsed clock signal by generating frequent pulsed clock signals with delays that do not overlap. By clustering the latches into numerous sub shifter registers and making use of latches, the shift register makes efficient use of a relatively small number of the pulsed clock signals (11) . The inputs and outputs of shift registers can be either parallel or serial.…”

Section: A Shift Registersmentioning

confidence: 99%

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A Low Power Shift Register Based on Pulsed Latch

Shankar,

Rohith

2024

IJST

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Objectives: To solve timing and power consumption issues in digital circuit design by creating a Low-Power Shift Register Based on Pulsed Latch (LPSR-PL). Targeting IoT sensors and portable devices for low-power operation, increase energy efficiency in shift registers by using numerous non-overlapping delayed pulsed clock signals, decoder-enabled design, and gated clock circuits. Methods: The work uses a unique strategy that decreases power consumption and timing difficulties by employing numerous non-overlapping delayed pulsed clock signals in the LPSR-PL. To improve data synchronisation, it combines latches into temporary store latches. The study uses a decoder-enabled design to compress control logic and simplify clock-pulse circuitry, resulting in power reductions. In addition, a gated clock circuit is designed to save energy by preventing pointless clock pulses during times of inactivity or static operation. Findings : The LPSR-PL is a good choice for contemporary digital circuit design as it efficiently addresses timing problems and reduces shift register power consumption. The employment of several non-overlapping delayed pulsed clock signals improves operating efficiency and data synchronisation. The employment of gated clock circuits, decoder-enabled architecture, and nonoverlapping clock signals has led to significant advancements in low-power shift register designs. For applications where energy conservation is crucial, such as Internet of Things sensors and portable devices, this technology provides a more energy-efficient option. The suggested model performs very well with a much reduced power usage of 0.502 µW. Novelty: Power consumption and timing accuracy have been problems with conventional shift registers for a very long time. Conventional methods' dependence on a single pulsed clock signal often produced inefficiencies and subpar results. The LPSR-PL, however, has altered the rules of the competition today by offering multiple non-overlapping delayed pulsed clock signals that signify a new era in digital circuits.

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Section: Existing Models Comparison Resultsmentioning

confidence: 99%

Section: A Shift Registersmentioning

confidence: 99%

A Low Power Shift Register Based on Pulsed Latch

Shankar,

Rohith

2024

IJST

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“…With the development of new process technology, the design method of FF continues to develop. Specific application requirements such as low voltage, low power, low cost or high performance also require new designs [ 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 ]. In this work, the FF design goal is a low voltage and low power consumption with a compact layout area design solution.…”

Section: Introductionmentioning

confidence: 99%

“…This gives a performance edge in power over the conventional TGFF design when the switching activity is lower. However, some internal floating nodes already exist, and use up to 24 transistors [ 20 , 21 ].…”

Section: Introductionmentioning

confidence: 99%

Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design

Lin

Hong

et al. 2022

Sensors

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A low-voltage and low-power true single-phase flip-flop that minimum the total transistor count by using the pass transistor logic circuit scheme is proposed in this paper. Optimization measures lead to a new flip-flop design with better various performances such as speed, power, energy, and layout area. Based on post-layout simulation results using the TSMC CMOS 180 nm and 90 nm technologies, the proposed design achieves the conventional transmission-gate-based flip-flop design with a 53.6% reduction in power consumption and a 63.2% reduction in energy, with 12.5% input data switching activity. In order to further the performance parameters of the proposed design, a shift-register design has been realized. Experimental measurements at 0.5 V/0.5 MHz show that this proposed design reduces power consumption by 47.3% while achieving a layout area reduction of 30.5% compared to the conventional design.

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A simultaneous area, delay and leakage current reduction method for Linear Feedback Shift Register (LFSR) using pulsed latches and DTMOS transistors

Munaf,

Ramashri

2024

e-Prime - Advances in Electrical Engineering, Electronics and E

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A Novel Cross-Latch Shift Register Scheme for Low Power Applications

Cited by 5 publications

References 33 publications

A Low Power Shift Register Based on Pulsed Latch

A Low Power Shift Register Based on Pulsed Latch

Low-Voltage and Low-Power True-Single-Phase 16-Transistor Flip-Flop Design

A simultaneous area, delay and leakage current reduction method for Linear Feedback Shift Register (LFSR) using pulsed latches and DTMOS transistors

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