A Novel DDFS Based on Trigonometric Approximation with a Scaling Block

Babak, Farhad; Keshavarzi, Parviz

doi:10.1109/itng.2009.165

Cited by 5 publications

(1 citation statement)

References 11 publications

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“…Using the sine-phase difference Niittylahti et al [6] proposes ROM reduced architecture for the DDFS. Another work by F. Babak et al [7] compressed the ROM size by 551.3:1 using trigonometric approximation with a scaling block. Designing a DDFS with frequency resolution in sub hertz range using the ROM-based architecture suffers from the huge power consumption, large area and more access time.…”

Section: Introductionmentioning

confidence: 99%

A novel low-latency, high-speed DDFS architecture

Hatai

Chakrabarti

2010

2010 Annual IEEE India Conference (INDICON)

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A recent trend in the research of ROM-less DDFS architecture, which is endowed with high speed, low power and high SFDR features and will generate the sine or cosine waveforms within a broad frequency range. In this work one high-speed, low-power, and low-latency (requires 11 clock cycles) pipelined ROM-less DDFS has been proposed and implemented in Xilinx Virtex-II Pro FPGA. The proposed ROM-less DDFS design has 32 bit phase input and 16 bit amplitude resolution with maximum amplitude error of u 4 1.5 10 . The FPGA implementation of the proposed design has an SFDR of -94.3 dBc and maximum operation frequency of 276 MHz by consuming only 22 K gate and 1.05 mW/MHz power. The high speed of operation and low power makes the propose design suitable for the use in communication transceiver for the up and down conversion..

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Section: Introductionmentioning

confidence: 99%