A Novel Design of Pipeline MDC-FFT Processor Based on Various Memory Access Mechanism

Yang, Jinjiang; Zhang, Dongming; Gong, Yu; Liu, Bo

doi:10.1109/cyberc.2016.20

Cited by 4 publications

(3 citation statements)

References 9 publications

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“…The throughput improvement with respect to [22] is approximately 1.2 GS/s and 3.3 GS/s for Virtex-5 (MOF=500 MHz) and Virtex-7 (MOF=740 MHz) respectively. In [12], [16] variable length FFT designs are presented for VLSI devices and in [23], [24] for FPGA devices. These designs reach few GS/s, as they are focused for WiMax and LTE applications, so they cannot meet the optical OFDM's throughput requirements.…”

Section: Fpga-implementation Resultsmentioning

confidence: 99%

FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems

Bruno

Almenar

Valls

2019

Microprocessors and Microsystems

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The transmission rate in current passive optical networks can be increased by employing Orthogonal Frequency Division Multiplexing (OFDM) modulation. The computational kernel of this modulation is the fast Fourier transform (FFT) operator, which has to achieve a very high throughput in order to be used in optical networks. This paper presents the implementation in an FPGA device of a variable-length FFT that can be configured in run-time to compute different FFT lengths between 16 and 1024 points. The FFT reaches a throughput of 10 GS/s in a Virtex-7 485T-3 FPGA device and was used to implement a 20 Gb/s optical OFDM receiver.

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Section: Fpga-implementation Resultsmentioning

confidence: 99%

FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems

Bruno

Almenar

Valls

2019

Microprocessors and Microsystems

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“…Therefore, The 8 banks of HXDSP104x would be divided into 4 group. The picture shows that our proposed addressing scheme outperform more than 54% in computation cycles compared to [14,17,15] when the FFT size is larger than 2048. The cycle costs may be a little higher compared with [16,18] when the size of FFT is small, it is just because the arithmetic units could not be made full used in such scale.…”

Section: Performance Evaluationmentioning

confidence: 97%

“…Common FFT processors can be classified into pipelined [6,15] and memorybased architectures [14,16,17,18,20]. The tradeoff between hardware overhead and speed is the main criterion for selection.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation of a conflict-free memory accessing technique for FFT on multicluster VLIW DSP

Zhang

et al. 2018

IEICE Electron. Express

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With the extensive application of signal processing, FFT on DSP processors evoke to be the trend. Aiming at solving the conflicts in memory accessing of these applications, an address generation technique called Mod-N Address is presented this paper. This scheme avoids the influence and conflicts of accessing to one specific bank at the same time. Instead, the data accessing pressure had been shared evenly into an independence block. Furthermore, a novel conflict-free memory-addressing scheme called Modulo-Block Scheduling (MBS) is proposed to ensure the continuous operation. We prove that the solution could achieve conflict-free accessing without extra time overhead and the unit had been implemented on our platform HXDSP104x. From the results, we can see that proposed unit achieves a 1.4 speed-up compared with the previous scheme, and experimental evaluations also show that the structure outperforms by an average of 8% to 54% compared with the conventional methods in performance.

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A high-speed single-path delay feedback pipeline FFT processor using vedic-multiplier

Gupta

Sharma

2017

2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC)

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A Novel Design of Pipeline MDC-FFT Processor Based on Various Memory Access Mechanism

Cited by 4 publications

References 9 publications

FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems

FPGA implementation of a 10 GS/s variable-length FFT for OFDM-based optical communication systems

Design and implementation of a conflict-free memory accessing technique for FFT on multicluster VLIW DSP

A high-speed single-path delay feedback pipeline FFT processor using vedic-multiplier

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