A Novel Design to Obtain Fault Tolerant Majority Gate for Five Input Majority Gate by Quantum Cellular Automata

Bhowmik, Dhrubajyoti; Saha, Apu Kr; Dutta, Paramartha

doi:10.1109/icmete.2016.114

Cited by 4 publications

(1 citation statement)

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“…The fundamental units of QCA are shown in Figure 1. Primary logic primitives, a majority gate and an inverter are found to be used in emerging nanotechnology based QCA [13][14][15][16]. Any QCA design can be realized using these two only taking with QCA wires along [17].…”

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confidence: 99%

Regular clocking scheme based design of cost-efficient comparator in QCA

Pal

Noorallahzadeh

Sharma

et al. 2021

IJEECS

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<span>Quantum-dot cellular automata (QCA) gained a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs had been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs have been facing the challenges of cost efficiency, power dissi-pation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposed a novel cost ef-fective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design was the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibited the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner was used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analyzed.</span>

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confidence: 99%