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<span>Quantum-dot cellular automata (QCA) gained a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs had been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs have been facing the challenges of cost efficiency, power dissi-pation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposed a novel cost ef-fective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design was the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibited the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner was used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analyzed.</span>

Quantum‐dot cellular automata (QCA) is gaining worldwide popularity due to its higher device concentration, lower power indulgence, and better switching speed. The information flows in QCA with the polarization state defined by the placement of electrons instead of current flow. The cell interaction principle under the influence of the clocking zone controls the cell placement during QCA circuit design. Most of the designs reported so far used random cell placement, which has no fabricating sense. Moreover, it is equally important for a cell placement algorithm to follow a realistic, regular underlying clocking scheme to maintain proper routing channels. In this regard, a systematic cell placement for the combinational logic circuit in QCA is proposed using the widely accepted underlying regular clocking scheme, universal, scalable and efficient (USE). The proposed method traverses all possible paths of a combinational logic circuit from output to input to build the desired circuit generating the automatic cell layout. A grid of clock zone of USE clock scheme is considered in the initial layout driving different paths of the circuit and finally evolves as the desired circuit. The generated automatic QCA layouts are competitive in occupied area, delay, and its cell count, which advocates the significance of such a scheme.

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