A Novel Digital Duty-Cycle Modulation Scheme for FPGA-Based Digital-to-Analog Conversion

Moffo, Bertrand Lonla; Mbihi, Jean

doi:10.1109/tcsii.2015.2407233

Cited by 10 publications

(2 citation statements)

References 5 publications

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“…where V C,0 is the initial voltage value of the capacitor, τ = RC is the time constant, b k represents the k th binary number and the sequence {b 1 , b 2 , …, b n } forms the binary code of the ReDAC. When the system operates at a precise and determinable frequency, if a sequence of binary codes is known, the output voltage value V C,n of the ReDAC can be solved according to the capacitor charging and discharging principle under (1) for the corresponding binary code. For the DAC, the aim is to output the specified voltage value, i.e.…”

Section: Uc-redac Mathematical Models and Architecturementioning

confidence: 99%

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An unconstrained relaxation digital‐to‐analog converter using optimal bit sequence

Zhang

et al. 2023

Electronics Letters

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Based on the relaxation digital‐to‐analog converter (ReDAC) architecture and the capacitor charge/discharge function under discrete time conditions, this paper proposes a new mathematical model for the output voltage of the ReDAC to implement the unconstrained relaxation DAC (Uc‐ReDAC). The system clock calibration is not required. An adaptive probabilistic binary particle swarm optimization (AP‐BPSO) algorithm is proposed for solving the binary coding configuration problem under the Uc‐ReDAC model. Simulation results show that the 8‐bit (10‐bit) Uc‐ReDAC has an average sampling rate of 7.9 MS/s (6.76 MS/s).

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Section: Uc-redac Mathematical Models and Architecturementioning

confidence: 99%

“…Introduction: Mostly digital DACs have attracted increasing attention from scholars due to their low power consumption, high system integration, and insensitivity to parasitic effects [1], and ReDAC is one of them [2].…”

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confidence: 99%

An unconstrained relaxation digital‐to‐analog converter using optimal bit sequence

Zhang

et al. 2023

Electronics Letters

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Software-Defined DDPM Modulators for D/A Conversion by General-Purpose Microcontrollers

2022

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The software implementation of Dyadic Digital Pulse Modulators (DDPMs) for Digital to Analog (D/A) conversion is addressed in this paper. In particular, an enhanced software DDPM implementation is proposed and compared with a plain, iterative software transposition of the basic DDPM hardware architecture. Experimental results on an 8-bit software-defined DDPM D/A converter implemented on a Texas Instrument c2000 microcontroller platform validate the approach, revealing for the novel optimized software DDPM a 6X maximum sample rate compared to the simple iterative implementation on the same microcontroller and at the same system clock frequency. Based on measurements, an 8-bit DDPM DAC featuring the proposed optimized implementation operates at 7.8kS/s with a maximum INL of 1.64LSB, a maximum DNL of 1.79LSB, an SFDR of 47.02dB and a SNDR of 45.27dB, corresponding to 7.23 ENOB, demonstrating the effectiveness and the applicability of the proposed approach to implement a low cost, software-defined D/A converters in microcontroller-based embedded systems.

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Emerging Relaxation and DDPM D/A Converters: Overview and Perspectives

Crovetti

Rubino

Abdullah

et al. 2022

2022 IEEE 65th International Midwest Symposium on Circuits and Systems (MWSCAS)

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A Novel Digital Duty-Cycle Modulation Scheme for FPGA-Based Digital-to-Analog Conversion

Cited by 10 publications

References 5 publications

An unconstrained relaxation digital‐to‐analog converter using optimal bit sequence

An unconstrained relaxation digital‐to‐analog converter using optimal bit sequence

Software-Defined DDPM Modulators for D/A Conversion by General-Purpose Microcontrollers

Emerging Relaxation and DDPM D/A Converters: Overview and Perspectives

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