A Novel DRAM Architecture for Improved Bandwidth Utilization and Latency Reduction Using Dual-Page Operation

Sudarshan, Chirag; Steiner, Lukas; Jung, Matthias; Lappas, Jan; Weis, Christian; Wehn, Norbert

doi:10.1109/tcsii.2021.3068007

Cited by 4 publications

(2 citation statements)

References 10 publications

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“…As the read operation in the g formed using NMOS transistor (M2), the worst read-access time was obser and SF process corners. Figure 15b shows the post-layout simulated read-ac voltage range from 0.9 to 1.2 V. At a supply voltage of 1.2 V, the eDRAM ca read-access time below 0.2 ns for the typical, best and worst process corners To demonstrate the eDRAM operation under various operating conditi out Monte Carlo mismatch simulations with 1000 trials were conducted, as ure 16. With operating frequencies of 100-667 MHz and TT, SF and FS pr the eDRAM operation was evaluated under supply voltages of 0.5-1.2 V and of −25 to 85 °C.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

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Pseudo-Static Gain Cell of Embedded DRAM for Processing-in-Memory in Intelligent IoT Sensor Nodes

Kim

Park

2022

Sensors

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This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an embedded dynamic random-access memory (eDRAM) macro for analog processing-in-memory (PIM). The proposed eDRAM cell consists of a two-transistor (2T) gain cell with a pseudo-static leakage compensation that maintains stored data without charge loss issue. Hence, the PS-GC can offer unlimited retention time in the same manner as static RAM (SRAM). Due to the extended retention time, bulky capacitors in conventional eDRAM are no longer needed, thereby, improving the area efficiency of eDRAM-based analog PIMs. The active leakage compensation of the PS-GC can effectively hold stored data even in a deep-submicron process that show significant leakage current. Therefore, the PS-GC can accelerate write-access time and read-access time without concern of increased leakage current. The proposed gain cell and its 64 × 64 eDRAM macro were implemented in a 28 nm CMOS process. The bitcell of the proposed gain cell has 0.79- and 0.58-times the area of those of 6T SRAM and 8T STAM, respectively. The post-layout simulation results demonstrate that the eDRAM maintains the pseudo-static operation with unlimited retention time successfully under wide range variations of process, voltage and temperature. At the operating frequency of 667 MHz, the eDRAM macro achieved an operating voltage range from 0.9 to 1.2 V and operating temperature range from −25 to 85 °C regardless of the process variation. The post-layout simulated write-access time and read-access time were below 0.3 ns at an operating temperature of 85 °C. The PS-GC consumes a static power of 2.2 nW/bit at an operating temperature of 25 °C.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

“…To overcome these limitations, PIMs with embedded dynamic random-access memory (eDRAM) have been proposed [11][12][13]. Logic-compatible eDRAMs [14][15][16][17] can offer a higher bit density and smaller area than those of the SRAMs. Hence, the eDRAM-based PIM can realize more area-efficient implementation than that of the SRAM-based PIM.…”

Section: Introductionmentioning

confidence: 99%