2016
DOI: 10.1109/jdt.2016.2561081
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A Novel Driving Method for High-Performance Amorphous Silicon Gate Driver Circuits in Flat Panel Display Industry

Abstract: In this work, we report a novel driving method to operate the amorphous silicon gate (ASG) driver circuits in flat panel display (FPD). The principal modification is to change the type of the clock signals to two low levels in the ASG circuit. The proposed ASG driver circuit has been implemented using a 5-mask amorphous silicon process for thin film transistors. The fall time of the output in the tested ASG circuit with the novel driving method is about 30% shorter than that with the conventional driving metho… Show more

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Cited by 8 publications
(4 citation statements)
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“…The ESD research of TFTs starts from the amorphous Si material. TFTs based on a-Si:H have been used in the fields of display driver [75,76] and sensor [77,78] due to their low processing temperature (<350 °C) and good homogeneity in large-scale production. However, TFTs are very vulnerable to ESD stress because they are fabricated on glass substrates.…”
Section: Esd Research Of Amorphous Si Based Tftsmentioning
confidence: 99%
“…The ESD research of TFTs starts from the amorphous Si material. TFTs based on a-Si:H have been used in the fields of display driver [75,76] and sensor [77,78] due to their low processing temperature (<350 °C) and good homogeneity in large-scale production. However, TFTs are very vulnerable to ESD stress because they are fabricated on glass substrates.…”
Section: Esd Research Of Amorphous Si Based Tftsmentioning
confidence: 99%
“…Because the gate signals generally have only two kinds of states, high and low states, the integration of the gate circuit is simpler than that of the source circuit for satisfying performance requirements. Because the active-matrix display should be replaced by high-mobility Si-based ICs [16], [17], double-rate driving and triple-rate driving methods for LCDs have already been developed and applied to products in order to reduce the cost of the source ICs [18], [19].…”
Section: Integrated Gate Driver Circuit Designmentioning
confidence: 99%
“…Therefore, to prevent the widening of the channel of the driving TFT, several methods, including multi-level clock modulation, the use of a low-leakage pull-down structure, and capacitive coupling, have been developed to increase the driving capability of the gate driver and thereby improve the delay of the scan pulse. The voltage modulation [12], [13] accelerates the charging and discharging to the output node of the gate driver by using clock signals with multiple voltage levels. This method generates a driver IC of great complexity, increasing the cost of the display.…”
Section: Introductionmentioning
confidence: 99%